Search results for "JHDL"

Found 17 publication records. Showing 17 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
143	Peter Bellows, Brad L. Hutchings	Designing Run-Time Reconfigurable Systems with JHDL.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGAs, image processing, CAD, configurable computing
105	Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting	A CAD Suite for High-Performance FPGA Design.	FCCM	1999	DBLP DOI BibTeX RDF	adaptive computing systems, high-performance FPGA design, FPGAs, configurable computing
92	Michael J. Wirthlin, Brian McMurtrey	IP delivery for FPGAs using Applets and JHDL.	DAC	2002	DBLP DOI BibTeX RDF	JHDL, FPGA, intellectual property, applet
80	David Castells-Rufas, Jordi Carrabina	Jumble: A Hardware-in-the-Loop Simulation System for JHDL.	FCCM	2007	DBLP DOI BibTeX RDF
63	Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner	Modeling and Prototyping of Communication Systems Using Java: A Case Study.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
63	Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner	JHDLBits: The Merging of Two Worlds.	FPL	2004	DBLP DOI BibTeX RDF
63	Brad L. Hutchings, Brent E. Nelson	Using general-purpose programming languages for FPGA design.	DAC	2000	DBLP DOI BibTeX RDF
39	Peter Bellows, Brad L. Hutchings	JHDL - An HDL for Reconfigurable Systems.	FCCM	1998	DBLP DOI BibTeX RDF
33	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri	Framework for Synthesis of Virtual Pipelines.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration
21	Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin	Design, Debug, Deploy: The Creation of Configurable Computing Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CAD for configurable computing, FPGA, design environments, configurable computing
21	Panagiotis D. Michailidis, Konstantinos G. Margaritis	Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Matthew French, Li Wang 0012, Michael J. Wirthlin	Power Visualization, Analysis, and Optimization Tools for FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
21	Brent E. Nelson	The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines.	ASAP	2006	DBLP DOI BibTeX RDF
21	Michael J. Wirthlin, Brian McMurtrey	Web-based IP evaluation and distribution using applets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Brad L. Hutchings, Brent E. Nelson	Unifying simulation and execution in a design environment for FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
21	Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin	Designing and Debugging Custom Computing Applications.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
21	Satnam Singh	Death of the RLOC?	FCCM	2000	DBLP DOI BibTeX RDF