Search results for "Response-Analyzer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
77	Makoto J. Hirayama, Toshiyuki Yamamoto	Network response analyzer system for interactive lectures in classroom or distance learning.	ICIS	2009	DBLP DOI BibTeX RDF	response analyzer, e-learning, local area network
26	Rupsa Chakraborty, Dipanwita Roy Chowdhury	coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips.	ACRI	2008	DBLP DOI BibTeX RDF	Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
26	Wen-Ben Jone, Sunil R. Das	Multiple-output parity bit signature for exhaustive testing.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	test response analyzer, Built-in self-test (BIST), design for testability
21	Baosheng Wang, Yuejian Wu, André Ivanov	Designs for Reducing Test Time of Distributed Small Embedded SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
21	Christian Dufaza, Hassan Ihs	A BIST-DFT technique for DC test of analog modules.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST
19	Tejas I. Dhamecha, Smit Marvaniya, Swarnadeep Saha, Renuka Sindhgatta, Bikram Sengupta	Balancing Human Efforts and Performance of Student Response Analyzer in Dialog-Based Tutors.	AIED (1)	2018	DBLP DOI BibTeX RDF
19	Luiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva	A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA.	LATS	2018	DBLP DOI BibTeX RDF
19	Manabu Ito, Motoki Miura	Handiness of device-free response analyzer systems in the classroom.	KES	2017	DBLP DOI BibTeX RDF
19	Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue	A fault tolerant response analyzer with self-error-correction capability.	ETS	2015	DBLP DOI BibTeX RDF
19	Hiroshi Kamada, Kazuaki Masuda, Keisuke Yamada	Automatic Response Analyzer with Multiple Choices in Classroom Using Image Processing and Cards.	ICGEC (1)	2015	DBLP DOI BibTeX RDF
19	Manabu Ito, Motoki Miura	Portable vision-based response analyzer with sheet bending recognition.	GCCE	2015	DBLP DOI BibTeX RDF
19	Yang Yu 0015, Zhiming Yang 0001, Xiyuan Peng, Dianguo Xu 0001	Efficient concurrent BIST with comparator-based response analyzer.	I2MTC	2013	DBLP DOI BibTeX RDF
19	Hsin-Wen Ting	An Output Response Analyzer Circuit for ADC Built-in Self-Test.	J. Electron. Test.	2011	DBLP DOI BibTeX RDF
19	Martin Ordonez, Maximiliano O. Sonnaillon, John E. Quaicoe, Mohammad Tariq Iqbal	An Embedded Frequency Response Analyzer for Fuel Cell Monitoring and Characterization.	IEEE Trans. Ind. Electron.	2010	DBLP DOI BibTeX RDF
19	Cleonilson Protásio de Souza, Francisco Marcos de Assis, Raimundo Carlos Silvério Freire	A New Architecture of Test Response Analyzer Based on the Berlekamp-Massey Algorithm for BIST.	IEEE Trans. Instrum. Meas.	2010	DBLP DOI BibTeX RDF
19	Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang	A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
19	Hao-Chiao Hong, Sheng-Chuan Liang	A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems.	ATS	2006	DBLP DOI BibTeX RDF
13	Jie Qin, Charles E. Stroud, Foster F. Dai	Noise Figure Measurement Using Mixed-Signal BIST.	ISCAS	2007	DBLP DOI BibTeX RDF
13	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski	Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.	ITC	2004	DBLP DOI BibTeX RDF
11	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
11	Mohammad Tehranipoor, Reza M. Rad	Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Ryo Nakai, Keizo Nagaoka	Conducting Classroom Discussions in the Manner of an Orchestra Using a Mobile Phone Based Response Analyzing System.	ICALT	2007	DBLP DOI BibTeX RDF
11	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
11	Premachandran R. Menon, Weifeng Xu, Russell Tessier	Design-specific path delay testing in lookup-table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi	An Optimized BIST Architecture for FPGA Look-Up Table Testing.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Mohammad Tehranipoor	Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.	DFT	2005	DBLP DOI BibTeX RDF
11	Yun-Che Wen	A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses.	VTS	2005	DBLP DOI BibTeX RDF
11	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Jerzy J. Dabrowski, Javier Gonzalez Bayon	Mixed Loopback BiST for RF Digital Transceivers.	DFT	2004	DBLP DOI BibTeX RDF
11	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.	VTS	2004	DBLP DOI BibTeX RDF
11	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
11	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
11	Hassan Ihs, Christian Dufaza	Test synthesis for DC test of switched-capacitors circuits.	ED&TC	1997	DBLP DOI BibTeX RDF