Search results for "path-delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
67	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
65	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
64	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
64	Irith Pomeranz, Sudhakar M. Reddy	Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
61	Xiaoxiao Wang 0001, Mohammad Tehranipoor, Ramyanshu Datta	Path-RO: a novel on-chip critical path delay measurement under process variations.	ICCAD	2008	DBLP DOI BibTeX RDF
57	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
57	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
57	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
54	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
52	Zhongcheng Li, Yinghua Min, Robert K. Brayton	A New Low-Cost Method for Identifying Untestable Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF	non-robustly untestable, Delay testing, path delay fault, implication
52	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
50	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay fault coverage, test set size, and performance trade-offs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
50	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
50	Wuudiann Ke, Premachandran R. Menon	Multifault testability of delay-testable circuits.	VTS	1995	DBLP DOI BibTeX RDF	delay-testable circuits, multifault testability, path-delay-fault testability, multiple stuck-at-fault testability, multilevel combinational circuits, robust path-delay-fault test set, logic testing, delays, combinational circuits, multivalued logic circuits
49	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
49	I-De Huang, Yi-Shing Chang, Sandeep K. Gupta 0001, Sreejit Chakravarty	An Industrial Case Study of Sticky Path-Delay Faults.	VTS	2008	DBLP DOI BibTeX RDF	sticky paths, timing false paths, path reprioritization, delay testing, test quality
48	Spyros Tragoudas, N. Denny	Path delay fault testing using test points.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing
46	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
45	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
45	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
45	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
44	Kwang-Ting Cheng, Hsi-Chuan Chen	Classification and identification of nonrobust untestable path delay faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
44	Premachandran R. Menon, Weifeng Xu, Russell Tessier	Design-specific path delay testing in lookup-table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
44	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
44	Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi	A Statistical Fault Coverage Metric for Realistic Path Delay Faults.	VTS	2004	DBLP DOI BibTeX RDF
42	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
42	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
40	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
40	Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz	On minimizing the number of test points needed to achieve complete robust path delay fault testability.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
39	Chung Liang Chen, Chung-Len Lee, Ming Shae Wu	A New Path Delay Test Scheme Based on Path Delay Inertia.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
39	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	New Parameter for Balancing Two Independent Measures in Routing Path.	ICCSA (4)	2004	DBLP DOI BibTeX RDF
37	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault-emulation, software-based testing, FPGA, path-delay
37	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	The optimistic update theorem for path delay testing in sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	test generation, Fault simulation, timing analysis, path delay faults
37	Stephan Eggersglüß, Rolf Drechsler	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.	ISMVL	2008	DBLP DOI BibTeX RDF	Boolean Encodings, ATPG, SAT, Path Delay Faults
37	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal
37	Shweta Chary, Michael L. Bushnell	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
37	Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu	An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.	PRDC	2002	DBLP DOI BibTeX RDF
36	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	Estimated Path Selection for the Delay Constrained Least Cost Path.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
35	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
35	Ramesh C. Tekumalla, Premachandran R. Menon	On Redundant Path Delay Faults in Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults
35	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
35	Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas	Low power ATPG for path delay faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults, PODEM
35	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	digital circuit testing, test generation, fault models, delay test, path delay faults
34	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
34	Karl Fuchs, Franz Fink, Michael H. Schulz	DYNAMITE: an efficient automatic test pattern generation system for path delay faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
34	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
34	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
34	Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri	NEST: a nonenumerative test generation method for path delay faults in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
34	Irith Pomeranz, Sudhakar M. Reddy	An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
34	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	High Quality Robust Tests for Path Delay Faults.	VTS	1997	DBLP DOI BibTeX RDF	test generation, fault modeling, delay test, robust test
34	Huawei Li 0001, Xiaowei Li 0001	Selection of Crosstalk-Induced Faults in Enhanced Delay Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG), crosstalk, delay test, critical paths
34	Srinivas Devadas, Kurt Keutzer	Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.	DAC	1990	DBLP DOI BibTeX RDF
34	Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss	Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.	VLSI Design	1999	DBLP DOI BibTeX RDF
33	Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001	Multiple Coupling Effects Oriented Path Delay Test Generation.	VTS	2008	DBLP DOI BibTeX RDF	crosstalk, delay test, path delay fault
33	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function
32	Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro	Efficient Path Selection for Delay Testing Based on Path Clustering.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	clustering, delay testing, delay fault, path delay
32	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
32	Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis	Concurrent Delay Testing in Totally Self-Checking Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators
32	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
32	Mukund Sivaraman, Andrzej J. Strojwas	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.	ICCAD	1996	DBLP DOI BibTeX RDF	fabrication process, coverage, delay testing, delay fault, path sensitization
32	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	On variable clock methods for path delay testing of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
32	Yuansong Qiao, Enda Fallon, Liam Murphy 0001, John Murphy 0001, Austin Hanley, Xiaosong Zhu, Adrian Matthews, Eoghan Conway, Gregory Hayes	SCTP Performance Issue on Path Delay Differential.	WWIC	2007	DBLP DOI BibTeX RDF	Retransmission strategy, Path difference, SCTP, Multi-homing
32	Irith Pomeranz, Sudhakar M. Reddy	Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
32	G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
32	Karl Fuchs, Michael Pabst, Torsten Rössel	RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
32	Irith Pomeranz, Sudhakar M. Reddy	Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.	VLSI Design	2005	DBLP DOI BibTeX RDF
32	Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik	Line coverage of path delay faults.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
32	Mukund Sivaraman, Andrzej J. Strojwas	Path delay fault diagnosis and coverage-a metric and an estimationtechnique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
31	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	On Balancing Delay and Cost for Routing Paths.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
31	David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran	Slope propagation in static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
31	Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
31	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
31	Jason Helge Anderson, Farid N. Najm	Switching activity analysis and pre-layout activity prediction for FPGAs.	SLIP	2003	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, power, estimation
30	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
30	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
30	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
30	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An efficient built-in self test method for robust path delay fault testing.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
30	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
30	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On local transformations and path delay fault testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	path delay fault model, testability preserving transformations, testability inproving transformations, design for testability
30	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
30	Harry Hengster, Rolf Drechsler, Bernd Becker 0001	On the application of local circuit transformations with special emphasis on path delay fault testability.	VTS	1995	DBLP DOI BibTeX RDF	local circuit transformations, path delay fault testability, SALT, logic testing, delays, integrated circuit testing, automatic testing
30	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
30	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
30	Soonhak Kwon, Kris Gaj, Chang Hoon Kim, Chun Pyo Hong	Efficient Linear Array for Multiplication in GF(2m) Using a Normal Basis for Elliptic Curve Cryptography.	CHES	2004	DBLP DOI BibTeX RDF	finite field, elliptic curve cryptography, Massey-Omura multiplier, Gaussian normal basis, critical path delay
30	Irith Pomeranz, Sudhakar M. Reddy	A Flexible Path Selection Procedure for Path Delay Fault Testing.	VTS	1999	DBLP DOI BibTeX RDF
30	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
29	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	Improving path delay testability of sequential circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
29	Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara	Efficient path delay test generation based on stuck-at test generation using checker circuitry.	ICCAD	2007	DBLP DOI BibTeX RDF
29	Bram Kruseman, Ananta K. Majhi, Guido Gronthoud	On Performance Testing with Path Delay Patterns.	VTS	2007	DBLP DOI BibTeX RDF
29	Cheng-Wen Wu, Chih-Yuang Su	A Probabilistic Model for Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
29	Mukund Sivaraman, Andrzej J. Strojwas	Primitive path delay faults: identification and their use in timinganalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
29	Huawei Li 0001, Zhongcheng Li, Yinghua Min	Reduction of Number of Paths to be Tested in Delay Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	linearly independent, analytical delay model, delay testing, path sensitization
29	Ming-Chien Tsai, Ching-Hwa Cheng	A full-synthesizable high-precision built-in delay time measurement circuit.	ASP-DAC	2009	DBLP DOI BibTeX RDF
29	Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang	An All-Digital High-Precision Built-In Delay Time Measurement Circuit.	VTS	2008	DBLP DOI BibTeX RDF
27	Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas	Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.	ISQED	2008	DBLP DOI BibTeX RDF
27	Maria K. Michael, Spyros Tragoudas	ATPG for Path Delay Faults without Path Enumeration.	ISQED	2001	DBLP DOI BibTeX RDF
27	Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal	Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF
27	Despina Triantafyllidou, Khaldoun Al Agha	The impact of path-delay routing on TCP in ad hoc networks.	IWCMC	2009	DBLP DOI BibTeX RDF	delay routing, route oscillations, MANET, TCP, OLSR