Search    Browse

The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Publications of "Mahabaleshwara" ( http://dblp.L3S.de/Authors/Mahabaleshwara )

  Author page on DBLP  Author page in RDF  Community of Mahabaleshwara in ASPL-2

Publication years (Num. hits)
2007 (1) 2012 (2)
Publication types (Num. hits)
article(2) inproceedings(1)
Venues (Conferences, Journals, ...)
IEEE J. Solid State Circuits(2) VLSI Design(1)
Authors
Mahabaleshwara(4) Kapil Vyas(3) Manish Jain(3) Navin K. Mishra(3) Amir Amirkhany(2) Arun Vaidyanath(2) Catherine Chen(2) Chanh Tran(2) Charlie Huang(2) Chris J. Madden(2) Dave Secker(2) Deborah Dressler(2) Gundlapalli Shanmukha Srinivas(2) H. Md. Shuaeb Fazeel(2) Jason Wei(2) Jie Shen 0010(2) More (+10 of total 43)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
No Growbag Graphs found.
Results
Found 4 publication records. Showing 3 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Kambiz Kaviani, Ting Wu 0003, Jason Wei, Amir Amirkhany, Jie Shen 0010, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi 0004, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen 0010, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu 0003, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #3 of 3 (100 per page; Change: )
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license