Search results for "21264"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey	Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha
86	Zarka Cvetanovic, Richard E. Kessler	Performance analysis of the Alpha 21264-based Compaq ES40 system.	ISCA	2000	DBLP DOI BibTeX RDF
51	Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson	Testability access of the high speed test features in the Alpha 21264 microprocessor.	ITC	1998	DBLP DOI BibTeX RDF
51	Michael K. Gowan, Larry L. Biro, Daniel B. Jackson	Power Considerations in the Design of the Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
48	Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger	Microprocessor pipeline energy analysis.	ISLPED	2003	DBLP DOI BibTeX RDF	alpha 21264, over-provisioning, power, energy, speculation
35	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
35	Juan L. Aragón, José González 0002, José M. García 0001, Antonio González 0001	Confidence Estimation for Branch Prediction Reversal.	HiPC	2001	DBLP DOI BibTeX RDF
33	Richard Weiss 0001, Nathan L. Binkert	A Comparison of AES Candidates on the Alpha 21264.	AES Candidate Conference	2000	DBLP BibTeX RDF
33	Richard E. Kessler	The Alpha 21264 microprocessor.	IEEE Micro	1999	DBLP DOI BibTeX RDF
33	Dilip K. Bhavsar	An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.	ITC	1999	DBLP DOI BibTeX RDF
33	Richard E. Kessler, Edward J. McLellan, D. A. Webb	The Alpha 21264 microprocessor architecture.	ICCD	1998	DBLP DOI BibTeX RDF
33	Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell	Timing verification of the 21264: A 600 MHz full-custom microprocessor.	ICCD	1998	DBLP DOI BibTeX RDF
33	Daniel L. Leibholz, Rahul Razdan	The Alpha 21264: a 500 MHz out-of-order execution microprocessor.	COMPCON	1997	DBLP DOI BibTeX RDF
33	Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan	Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor.	ICCD	1997	DBLP DOI BibTeX RDF
31	Yossi Malka, Avi Ziv	Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha
17	Cor Meenderinck, Ben H. H. Juurlink	(When) Will CMPs Hit the Power Wall?.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
17	Sangeetha Sudhakrishnan, Liying Su, Jose Renau	Processor Verification with hwBugHunt.	ISQED	2008	DBLP DOI BibTeX RDF
17	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
17	Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein	Timing analysis for full-custom circuits using symbolic DC formulations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Aaron Smith, Jon Gibson, Bertrand A. Maher, Nicholas Nethercote, Bill Yoder, Doug Burger, Kathryn S. McKinley, James H. Burrill	Compiling for EDGE Architectures.	CGO	2006	DBLP DOI BibTeX RDF
17	R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein	Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Joon-Sang Park, Michael Penner, Viktor K. Prasanna	Optimizing Graph Algorithms for Improved Cache Performance.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Cache-friendly algorithms, shortest path, graph algorithms, minimum spanning trees, graph matching, algorithm performance, cache-oblivious algorithms, data layout optimizations
17	Lu Peng 0001, Jih-Kwon Peir, Konrad Lai	Signature Buffer: Bridging Performance Gap between Registers and Caches.	HPCA	2004	DBLP DOI BibTeX RDF
17	Peter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz 0001	SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
17	Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra	Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.	ICCD	2004	DBLP DOI BibTeX RDF
17	Christophe Lemuet, William Jalby, Sid Ahmed Ali Touati	Improving Load/Store Queues Usage in Scientific Computing.	ICPP	2004	DBLP DOI BibTeX RDF
17	David Parello, Olivier Temam, Albert Cohen 0001, Jean-Marie Verdun	Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors.	SC	2004	DBLP DOI BibTeX RDF
17	Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan	Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.	ICCD	2003	DBLP DOI BibTeX RDF
17	Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein	Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.	ICCD	2003	DBLP DOI BibTeX RDF
17	Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies	Testability Features of the Alpha 21364 Microprocessor.	ITC	2003	DBLP DOI BibTeX RDF
17	Mondira Deb Pant, Pankaj Pant, D. Scott Wills	On-chip decoupling capacitor optimization using architectural level prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
17	Daniel A. Jiménez, Calvin Lin	Neural methods for dynamic branch prediction.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	neural networks, Branch prediction
17	Kazuto Matsuo, Jinhui Chao, Shigeo Tsujii	An Improved Baby Step Giant Step Algorithm for Point Counting of Hyperelliptic Curves over Finite Fields.	ANTS	2002	DBLP DOI BibTeX RDF
17	Joon-Sang Park, Michael Penner, Viktor K. Prasanna	Optimizing Graph Algorithms for Improved Cache Performance.	IPDPS	2002	DBLP DOI BibTeX RDF
17	Chi-Keung Luk, Robert Muth, Harish Patil, Richard Weiss 0001, P. Geoffrey Lowney, Robert S. Cohn	Profile-guided post-link stride prefetching.	ICS	2002	DBLP DOI BibTeX RDF	address strides, post-link optimizations, profiling, data prefetching, memory latency
17	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
17	Daniel A. Jiménez, Heather L. Hanson, Calvin Lin	Boolean Formula-Based Branch Prediction for Future Technologies.	IEEE PACT	2001	DBLP DOI BibTeX RDF
17	Christopher T. Weaver, Todd M. Austin	A Fault Tolerant Approach to Microprocessor Design.	DSN	2001	DBLP DOI BibTeX RDF
17	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
17	Dilip K. Bhavsar, Rishan Tan	Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
17	R. Iris Bahar, Srilatha Manne	Power and energy reduction via pipeline balancing.	ISCA	2001	DBLP DOI BibTeX RDF
17	Lisa Wu 0001, Christopher T. Weaver, Todd M. Austin	CryptoManiac: a fast flexible architecture for secure communication.	ISCA	2001	DBLP DOI BibTeX RDF
17	Kazumaro Aoki, Fumitaka Hoshino, Tetsutaro Kobayashi	A Cyclic Window Algorithm for ECC Defined over Extension Fields.	ICICS	2001	DBLP DOI BibTeX RDF
17	Roberto Maro, Yu Bai 0001, R. Iris Bahar	Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.	PACS	2000	DBLP DOI BibTeX RDF	low-power, high-performance, architecture-level
17	Kourosh Gharachorloo, Madhu Sharma, Simon Steely, Stephen Van Doren	Architecture and design of AlphaServer GS320.	ASPLOS	2000	DBLP DOI BibTeX RDF