Search results for "Adder/subtractor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
60	Himanshu Thapliyal	Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates.	Trans. Comput. Sci.	2016	DBLP DOI BibTeX RDF
46	Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin 0001	Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system
44	Keshab K. Parhi	Low-energy CSMT carry generators and binary adders.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
37	Ahmad Karimi, Keivan Navi	The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology.	Comput. Electr. Eng.	2024	DBLP DOI BibTeX RDF
37	Yuan Gao, Bayan Omar Mohammed	A new applicable and multilayer design of nanoscale adder-subtractor using quantum-dots.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
37	Bianca Silveira, Guilherme Paim, Brunno Alves Abreu, Rafael dos Santos Ferreira, Cláudio Machado Diniz, Eduardo Antônio César da Costa, Sergio Bampi	The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
37	Ashish Reddy Bommana, Srinivas Boppu	A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization.	MCSoC	2022	DBLP DOI BibTeX RDF
37	Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast	A novel reversible ternary coded decimal adder/subtractor.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
37	Mukesh Patidar, Namit Gupta	Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder-subtractor using QCA technology.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
37	Mohamed Osman, Khaled El-Wazan	Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q.	Symmetry	2021	DBLP DOI BibTeX RDF
37	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation.	J. Electr. Comput. Eng.	2021	DBLP DOI BibTeX RDF
37	Mário P. Véstias, Horácio C. Neto	Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor.	Algorithms	2021	DBLP DOI BibTeX RDF
37	Nuriddin Safoev, Jun-Cheol Jeon	Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
37	E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS).	iSES	2020	DBLP DOI BibTeX RDF
37	Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan	High Speed Controllable Inverter for Adder-Subtractor in QCA.	ICCCNT	2019	DBLP DOI BibTeX RDF
37	Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi	A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates.	Integr.	2018	DBLP DOI BibTeX RDF
37	Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast	Design of a parity preserving reversible full adder/subtractor circuit.	Int. J. Comput. Intell. Stud.	2018	DBLP DOI BibTeX RDF
37	Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani	Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
37	Manish Kumar Jaiswal, Hayden Kwok-Hay So	Architecture Generator for Type-3 Unum Posit Adder/Subtractor.	ISCAS	2018	DBLP DOI BibTeX RDF
37	Ghassem Jaberipur, Armin Belghadr	(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling.	Comput. Electr. Eng.	2017	DBLP DOI BibTeX RDF
37	Rasha Montaser, Ahmed Younes, Mahmoud A. Abdel-Aty	New Design of Reversible Full Adder/Subtractor using R gate.	CoRR	2017	DBLP BibTeX RDF
37	Praveena Murugesan, Thanushkodi Keppanagounder, Vijeyakumar Krishnasamy Natarajan	Design of Efficient Reversible BCD Adder-Subtractor Architecture and Its Optimization Using Carry Skip Logic.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
37	Mohammad Hossein Moaiyeri, Elham Taherkhani, Shaahin Angizi	A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology.	CoRR	2016	DBLP BibTeX RDF
37	Vandana Shukla, O. P. Singh, Ganga Ram Mishra, Raj Kumar Tiwari	Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach.	ICIIS	2016	DBLP DOI BibTeX RDF
37	Milad Sangsefidi, Morteza Karimpour, Mahdiyar Sarayloo	Efficient Design of a Coplanar Adder/Subtractor in Quantum-Dot Cellular Automata.	EMS	2015	DBLP DOI BibTeX RDF
37	Nusrat Jahan Lisa, Hafiz Md. Hasan Babu	Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing.	ISMVL	2015	DBLP DOI BibTeX RDF
37	Thian Fatt Tay, Chip-Hong Chang	A new unified modular adder/subtractor for arbitrary moduli.	ISCAS	2015	DBLP DOI BibTeX RDF
37	Moein Kianpour, Reza Sabbaghi-Nadooshan, Keivan Navi	A novel design of 8-bit adder/subtractor by quantum-dot cellular automata.	J. Comput. Syst. Sci.	2014	DBLP DOI BibTeX RDF
37	Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan	Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.	Trans. Comput. Sci.	2014	DBLP DOI BibTeX RDF
37	Sayeeda Sultana, Katarzyna Radecka	Testing reversible adder/subtractor for missing control points.	MWSCAS	2013	DBLP DOI BibTeX RDF
37	Purnima Sethi, Sukhdev Roy	All-Optical Ultrafast Adder/Subtractor and MUX/DEMUX Circuits with Silicon Microring Resonators.	OSC	2012	DBLP DOI BibTeX RDF
37	Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Unified Architecture for BCD and Binary Adder/Subtractor.	DSD	2011	DBLP DOI BibTeX RDF
37	Osama Daifallah Al-Khaleel, Mohammad Al-Khaleel, Zakaria Al-Qudah, Christos A. Papachristou, Khaldoon Mhaidat, Francis G. Wolff	Fast binary/decimal adder/subtractor with a novel correction-free BCD addition.	ICECS	2011	DBLP DOI BibTeX RDF
37	H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, K. B. Raja	Low Power Reversible Parallel Binary Adder/Subtractor	CoRR	2010	DBLP BibTeX RDF
37	Lamiaa Sayed Abdel Hamid, Khaled Ali Shehata, Hassan El-Ghitani, Mohamed ElSaid	Design of Generic Floating Point Multiplier and Adder/Subtractor Units.	UKSim	2010	DBLP DOI BibTeX RDF
37	Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas	A High Performance Unified BCD and Binary Adder/Subtractor.	ISVLSI	2009	DBLP DOI BibTeX RDF
37	Mozammel H. A. Khan	A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry.	J. Syst. Archit.	2008	DBLP DOI BibTeX RDF
37	Mozammel H. A. Khan, Marek A. Perkowski	Quantum ternary parallel adder/subtractor with partially-look-ahead carry.	J. Syst. Archit.	2007	DBLP DOI BibTeX RDF
37		A Fast Combined Decimal Adder/Subtractor	CoRR	2005	DBLP BibTeX RDF
37	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.	ESA	2005	DBLP BibTeX RDF
37	Ashok K. Goel 0002, Frederick Damstra, Brent K. Jesiek	Gallium arsenide based floating point adder/subtractor.	CATA	1998	DBLP BibTeX RDF
36	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE (4)	2008	DBLP DOI BibTeX RDF
36	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
28	Sabyasachi Das, Sunil P. Khatri	Resource sharing among mutually exclusive sum-of-product blocks for area reduction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF
28	Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale	Design guidelines for reconfigurable multiplier blocks.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
28	Richard I. Hartley, Albert E. Casavant	Optimizing pipelined networks of associative and commutative operators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
28	David A. Basin, Peter Del Vecchio	Verification Of Combinational Logic in Nuprl.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF