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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 26 occurrences of 21 keywords
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Results
Found 32 publication records. Showing 31 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
102 | Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens |
Reversible online BIST using bidirectional BILBO. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
bilbo, bist, testing, reversible logic |
102 | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer |
Generating a family of testable designs using the BILBO methodology. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
BILBO design system, built-in self-test, test scheduling, synthesis for testability |
63 | G. M. Beumer, Qian Tao, Asker M. Bazen, Raymond N. J. Veldhuis |
A Landmark Paper in Face Recognition. |
FGR |
2006 |
DBLP DOI BibTeX RDF |
face registration, Viola-Jones, landmark correction, face recognition, landmarking, likelihood ratio |
63 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
63 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A Novel BIST Architecture With Built-in Self Check. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
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51 | Rachel Bilbo, Zhi Li, Kendal Norman, Gautam Golwala, Sathya Sundaram, Perry Lee, Jan P. Allebach |
Understanding fashion aesthetics: training a neural network based predictor using popularity scores. |
IQSP |
2019 |
DBLP DOI BibTeX RDF |
|
42 | Albrecht P. Stroele, Hans-Joachim Wunderlich |
Hardware-optimal test register insertion. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
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42 | Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha |
Automatic Insertion of BIST Hardware Using VHDL. |
DAC |
1988 |
DBLP BibTeX RDF |
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42 | Andrzej Krasniewski, Alexander Albicki |
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
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32 | Xuedong Li, Walter Yuan, Dezhong Peng, Qiaozhu Mei, Yue Wang 0035 |
When BERT meets Bilbo: a learning curve analysis of pretrained language model on disease classification. |
BMC Medical Informatics Decis. Mak. |
2021 |
DBLP DOI BibTeX RDF |
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32 | Xuedong Li, Walter Yuan, Dezhong Peng, Qiaozhu Mei, Yue Wang 0035 |
When BERT Meets Bilbo: A Learning Curve Analysis of Pretrained Language Model on Disease Classification. |
ICHI |
2020 |
DBLP DOI BibTeX RDF |
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32 | Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi |
BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding. |
CoRR |
2017 |
DBLP BibTeX RDF |
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32 | Amal Htait, Sébastien Fournier, Patrice Bellot |
Bilbo-Val: Automatic Identification of Bibliographical Zone in Papers. |
LREC |
2016 |
DBLP BibTeX RDF |
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32 | Abdelhakim Latoui, Farid Djahli |
An Optical BILBO for Online Testing of Embedded Systems. |
IEEE Des. Test |
2013 |
DBLP DOI BibTeX RDF |
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32 | Young-Min Kim, Patrice Bellot, Jade Tavernier, Elodie Faath, Marin Dacos |
Evaluation of BILBO reference parsing in digital humanities via a comparison of different tools. |
ACM Symposium on Document Engineering |
2012 |
DBLP DOI BibTeX RDF |
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32 | Kazuteru Namba, Hideo Ito |
Construction of BILBO FF with Soft-Error-Tolerant Capability. |
IEICE Trans. Inf. Syst. |
2011 |
DBLP DOI BibTeX RDF |
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32 | Kazuteru Namba, Hideo Ito |
Soft Error Tolerant BILBO FF. |
DFT |
2010 |
DBLP DOI BibTeX RDF |
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32 | Ioannis Voyiatzis, Dimitris Kehagias |
A SiC Pair Generator for a Bilbo Environment. |
J. Circuits Syst. Comput. |
2006 |
DBLP DOI BibTeX RDF |
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32 | Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia |
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. |
VLSI Design |
1992 |
DBLP DOI BibTeX RDF |
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32 | M. Martinez, N. P. Cagigal, Salvador Bracho |
Arithmetical logical unit design for a processor with BILBO techniques: Functional simulation and test strategies. |
Microprocessing and Microprogramming |
1990 |
DBLP DOI BibTeX RDF |
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32 | Andrzej Krasniewski, Alexander Albicki |
Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. |
ITC |
1985 |
DBLP BibTeX RDF |
|
28 | Albrecht P. Stroele, Hans-Joachim Wunderlich |
Test register insertion with minimum hardware cost. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
test register insertion, BILBO, CBILBO, Built-in self-test |
28 | Peter D. Hortensius, Robert D. McLeod, Howard C. Card |
Cellular Automata-Based Signature analysis for Built-in Self-Test. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
signature analysis properties, one-dimensional cellular automata, cyclic-group rules, CALBO, cellular automata-based logic block observation, BILBO, built-in block observation, logic testing, built-in self-test, built-in self test, LFSR, linear feedback shift register, finite automata, test pattern generation |
28 | Thomas W. Williams, Kenneth P. Parker |
Design for Testability - A Survey. |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path |
21 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
An Improved Soft-Error Rate Measurement Technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
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21 | Doaa A. Nassar, Aly E. Salama |
A heuristic DSP BIST insertion algorithm with minimum area overhead. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
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21 | Aiman H. El-Maleh, Yahya E. Osais |
A retiming-based test pattern generator design for built-in self test of data path architectures. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
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21 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Efficient Implementation of Multiple On-Chip Signature Checking. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
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21 | Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha |
BIDES: A BIST design expert system. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
knowledge-based expert system, Built-in self-test, design for testability, pseudorandom testing |
21 | Andrzej Krasniewski, Slawomir Pilarski |
Circular self-test path: a low-cost BIST technique for VLSI circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
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21 | Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto |
ESTA: an expert system for DFT rule verification. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
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