Search results for "Backtrace"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
140	Ramakrishna Voorakaranam, Abhijit Chatterjee	Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.	ARVLSI	1999	DBLP DOI BibTeX RDF	analog verification, fault diagnosis, test generation, analog testing, Backtrace
120	Martin Stáva, Ondrej Novák	Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.	DSD	2006	DBLP DOI BibTeX RDF	FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace
86	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
74	Alfred V. Gomes, Abhijit Chatterjee	Robust optimization based backtrace method for analog circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
47	Kim T. Le, Kewal K. Saluja	A Heuristic Measure to Maximize Detected Faults per Test.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	combinational circuit testing, dynamic test compaction, fault selection, test generation, testability measures, backtrace
47	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
40	Rajesh Ramadoss, Michael L. Bushnell	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
40	Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang	Computation of floating mode delay in combinational circuits: practice and implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
34	Jingling Zhao, Congxiang Yu, Yunze Ni	A Universal Defense System Based on Backtrace Canary for ELF Against Vulnerabilities.	AINA	2020	DBLP DOI BibTeX RDF
34	Lee Aaron Newberg	Memory-efficient dynamic programming backtrace and pairwise local sequence alignment.	Bioinform.	2008	DBLP DOI BibTeX RDF
34	Martin Stáva, Ondrej Novák	HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration.	DDECS	2006	DBLP DOI BibTeX RDF
34	Chao Liu 0001, Xifeng Yan, Hwanjo Yu, Jiawei Han 0001, Philip S. Yu	Mining Behavior Graphs for "Backtrace" of Noncrashing Bugs.	SDM	2005	DBLP DOI BibTeX RDF
34	Andrei Mekler, Jaan Raik	Multiple-objective backtrace for solving test generation constraints.	SoC	2003	DBLP DOI BibTeX RDF
34	Antonio Lioy	Adaptative backtrace and dynamic partitioning enhance ATPG.	ICCD	1988	DBLP DOI BibTeX RDF
27	Dong Shi, Xinming Zhang 0001, Wenbo Zhu, Enbo Wang	RCDS: A Ranking-Based Algorithm to Compute the CDS of the Ad Hoc Networks.	NCM (1)	2008	DBLP DOI BibTeX RDF	ad hoc networks, broadcast, connected dominating set, backtrace
27	Hideo Fujiwara, Takeshi Shimono	On the Acceleration of Test Generation Algorithms.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults
20	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel fault backtracing for calculation of fault coverage.	ASP-DAC	2008	DBLP DOI BibTeX RDF
20	Jing Yang 0003, Mary Lou Soffa, Leo Selavo, Kamin Whitehouse	Clairvoyant: a comprehensive source-level debugger for wireless sensor networks.	SenSys	2007	DBLP DOI BibTeX RDF	embedded debugging, wireless sensor networks, distributed debugging, source-level debugging
20	Andrew M. Cheadle, A. J. Field, J. W. Ayres, Neil Dunn, Richard A. Hayden, Johan Nyström-Persson	Visualising dynamic memory allocators.	ISMM	2006	DBLP DOI BibTeX RDF	visualisation of objects, garbage collection, memory management, dynamic memory allocation, language implementation
20	Hanhua Chen, Hai Jin 0001	Identifying Community Structure in Semantic Peer-to-Peer Networks.	SKG	2006	DBLP DOI BibTeX RDF
20	Wojciech Bozejko, Mieczyslaw Wodecki	Solving the Flow Shop Problem by Parallel Tabu Search.	PARELEC	2002	DBLP DOI BibTeX RDF
20	Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang	Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.	DFT	2002	DBLP DOI BibTeX RDF
20	M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff	A New Test Generation Approach for Embedded Analogue Cores in SoC.	ITC	2002	DBLP DOI BibTeX RDF
20	Ramakrishna Voorakaranam, Abhijit Chatterjee	Hierarchical Test Generation for Analog Circuits Using Incremental Test Development.	VTS	1999	DBLP DOI BibTeX RDF
20	Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min	Memory Efficient ATPG for Path Delay Faults.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization
20	Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler	A hierarchical test pattern generation system based on high-level primitives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
20	Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert	SOCRATES: a highly efficient automatic test pattern generation system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
20	M. Ladjadj, John F. McDonald 0001	Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits.	DAC	1987	DBLP DOI BibTeX RDF