Search results for "Boundary-Scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora	A Structured Graphical Tool for Analyzing Boundary Scan Violations.	ITC	2002	DBLP DOI BibTeX RDF
103	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
85	Thomas A. Ziaja, Earl E. Swartzlander Jr.	Boundary scan in board manufacturing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Board and system test, boundary scan description language, design-for-test, boundary scan
82	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
74	T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
70	José M. Miranda	A BIST and Boundary-Scan Economics Framework.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
70	Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski	BIST of PCB interconnects using boundary-scan architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
69	Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian	Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	relay propagation test, multiprocessor systems, Boundary scan
67	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
64	Andrzej Rucinski 0002, Barbara Dziurla-Rucinska	Boundary Scan as a Test Solution in Microelectronics Curricula.	DELTA	2002	DBLP DOI BibTeX RDF	IEEE 1149.4 standard, Education, Boundary scan
61	Tian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh	Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks.	VTS	2004	DBLP DOI BibTeX RDF
60	Jung-Cheun Lien, Melvin A. Breuer	An optimal scheduling algorithm for testing interconnect using boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Boundary scan, test scheduling, interconnect test
60	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
60	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang	Broadcasting test patterns to multiple circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
59	Kenneth P. Parker	Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?	ITC	2003	DBLP DOI BibTeX RDF
59	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
55	Maciej Nikodem	Boundary Scan Security Enhancements for a Cryptographic Hardware.	EUROCAST	2009	DBLP DOI BibTeX RDF	IEEE 1149, side-channel attacks, countermeasures, boundary scan
55	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Novel Control Pattern Generators for Interconnect Testing with Boundary Scan.	DFT	1999	DBLP DOI BibTeX RDF	BIST, boundary scan, Interconnect testing
55	Bernhard Eschermann	An implicitly testable boundary scan TAP controller.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	test controller, BIST, self-test, boundary scan, synthesis for testability, controller design
55	Kenneth P. Parker, Stig Oresjo	A language for describing boundary scan devices.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	boundary scan testability, VHDL
53	Wang-Dauh Tseng, Kuochen Wang	Testable Design and Testing of MCMs Based on Multifrequency Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module
52	Luís Santos 0005, Mário Zenha Rela	Constraints on the Use of Boundary-Scan for Fault Injection.	LADC	2003	DBLP DOI BibTeX RDF
51	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Testing SoC Interconnects for Signal Integrity Using Boundary Scan.	VTS	2003	DBLP DOI BibTeX RDF	Integrity Loss Sensor, System-on-Chip Interconnects, Data Compression, Boundary Scan, Signal Integrity
51	Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting	Syndrome Simulation And Syndrome Test For Unscanned Interconnects.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	unscanned interconnects, syndrome test methodology, event driven syndrome simulation, boundary scan environment, faulty syndromes, fault-free syndromes, tolerable error rate, partially scanned PCB, board level testing, test pattern generation, boundary scan testing, test length, MCM, set covering problem, simulation algorithm, weighted random patterns, test cost reduction
51	Tong Liu 0007, Fabrizio Lombardi, José Salinas	Diagnosis of interconnects and FPICs using a structured walking-1 approach.	VTS	1995	DBLP DOI BibTeX RDF	field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
49	Frank P. Higgins, Rajagopalan Srinivasan	BSM2: Next Generation Boundary-Scan Master.	VTS	2000	DBLP DOI BibTeX RDF
48	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
48	Matthew L. Fichtenbaum, Gordon D. Robinson	Scan test architectures for digital board testers.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	tester architecture, scan, boundary scan
47	Janusz Rajski, Jerzy Tyszer, Nadime Zacharia	Test Data Decompression for Multiple Scan Designs with Boundary Scan.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	reseeding of LFSRs, multiple scan chains, test data decompression, built-in self-test, design for testability, Boundary scan, scan-based designs
46	Wuudiann Ke	Hybrid Pin Control Using Boundary-Scan And Its Applications.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Boundary-Scan (B-S), Hybrid Pin Control, Fault Injection, Delay Test
46	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
46	Don Sterba, Andy Halliday, Don McClean	ATPG and diagnostics for boards implementing boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	1149.1, ATPG, diagnostics, boundary scan, JTAG
46	R. G. Bennetts, A. Osseyran	IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	device test, board test, 1149.1, boundary scan
46	Frans Jong, José S. Matos, José M. Ferreira	Boundary scan test, test methodology, and fault modeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	BST-net, PCB testing, diagnosis, fault modeling, test-pattern generation, boundary scan test
46	Colin M. Maunder, Rodham E. Tulloss	An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	ANSI/IEEE Std 1149.1, loaded-board test, self-test, boundary scan, JTAG
45	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
44	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
43	Jeff Rearick, Sylvia Patterson, Krista Dorner	Integrating Boundary Scan into Multi-GHz I/O Circuitry.	ITC	2004	DBLP DOI BibTeX RDF
43	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
43	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
43	W. David Ballew, Lauren M. Streb	Board-level boundary scan: regaining observability with an additional IC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
43	R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg	Designing and Implementing an Architecture with Boundary Scan.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
41	Dilip K. Bhavsar	Testing Interconnections to Static RAMs.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
39	Mário Zenha Rela, João Carlos Cunha, Carlos Bruno Silva, Luís Ferreira da Silva	On the Effects of Errors During Boot.	LADC	2005	DBLP DOI BibTeX RDF	fault-tolerance, embedded systems, fault-injection, boundary-scan, dependability evaluation
35	Kaushik De	Test methodology for embedded cores which protects intellectual property.	VTS	1997	DBLP DOI BibTeX RDF	core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
34	Tapan J. Chakraborty	Efficient Test Architecture based on Boundary Scan for Comprehensive System Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
34	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	ITC	2002	DBLP DOI BibTeX RDF
34	Mike Wondolowski, Ben Bennetts, Adam W. Ley	Boundary Scan: The Internet of Test.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
34	Bulent I. Dervisoglu, Mike Ricchetti, William Eklow	Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.	ITC	1998	DBLP DOI BibTeX RDF
34	Kanad Chakraborty, Pinaki Mazumder	A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.	ED&TC	1997	DBLP DOI BibTeX RDF
32	Ben Bennetts	Essential reading for the basics and implementation of boundary scan: Parker, K PThe boundary-scan handbook Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9270 1, £48.00/Dfl. 160.00, pp 282.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
32	Yoon-Hwa Choi, Taechul Jung	Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices.	ICCAD	1992	DBLP DOI BibTeX RDF
32	Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani	Extending JTAG for Testing Signal Integrity in SoCs.	DATE	2003	DBLP DOI BibTeX RDF
30	Tapan J. Chakraborty, Chen-Huan Chiang	A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.	ITC	2002	DBLP DOI BibTeX RDF
30	Bulent I. Dervisoglu	Boundary-Scan Update: IEEE P1149.2 Description and Status Report.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
30	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	An Embedded IDDQ Testing Architecture and Technique.	ISQED	2003	DBLP DOI BibTeX RDF	IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
30	Hans A. R. Manhaeve, Stefaan Kerckenaere	An On-Chip Detection Circuit for the Verification of IC Supply Connections.	DFT	2001	DBLP DOI BibTeX RDF	IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor
30	Najmi T. Jarwala	Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	module test, design-for-testability, boundary-scan
30	Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida	Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	core test, design-for-testability, BIST, scan, boundary scan, test bus
30	Nur A. Touba, Bahram Pouya	Testing Embedded Cores Using Partial Isolation Rings.	VTS	1997	DBLP DOI BibTeX RDF	Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
30	Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu	Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	MTM Bus, Boundary Scan, Hierarchical Testing
30	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer	A Design For Test Perspective on I/O Management.	ICCD	1996	DBLP DOI BibTeX RDF	I/O pads, High Level Synthesis, Design For Test, Boundary Scan
29	Jing Wang, Shengbing Zhang, Zhang Meng	Testing of a 32-bit High Performance Embedded Microprocessor.	SIES	2007	DBLP DOI BibTeX RDF
29	Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch	An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.	APCCAS	2006	DBLP DOI BibTeX RDF
26	Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin	Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
26	Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri	Test-mode-only scan attack using the boundary scan chain.	ETS	2014	DBLP DOI BibTeX RDF
26	Stephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood	Hierarchical boundary-scan: a Scan Chip-Set solution.	ITC	2001	DBLP DOI BibTeX RDF
26	Anthony P. Ambler	The application and use of boundary scan: Bleeker, H, van den Eijnden, P and de Jong, FBoundary-scan test - a practical approach Kluwer Academic (1992) ISBN 0 7923 9296 5, £50.75, pp 222.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
25	Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela	FPGA-Based Boundary-Scan Bist.	FPL	2006	DBLP DOI BibTeX RDF
25	Yang Jiangping, Li Guixiang, Wang Wanglei	A model of VLSI interconnect test based on boundary scan.	ICARCV	2004	DBLP DOI BibTeX RDF
25	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
25	Bradford G. Van Treuren, José M. Miranda	Embedded Boundary Scan.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
25	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity.	ICCD	2003	DBLP DOI BibTeX RDF
25	Tek Jau Tan, Chung-Len Lee	Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment.	VTS	2001	DBLP DOI BibTeX RDF	Oscillation test, Delay testing, System test, SOC testing, Embedded testing
25	Sungju Park, Taehyung Kim	A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects.	DATE	2000	DBLP DOI BibTeX RDF
25	Hyunjin Kim, Jongchul Shin, Sungho Kang 0001	An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment.	ICCD	1999	DBLP DOI BibTeX RDF
25	Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud	Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access.	VTS	1999	DBLP DOI BibTeX RDF
25	Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur	Delay test of chip I/Os using LSSD boundary scan.	ITC	1998	DBLP DOI BibTeX RDF
25	Adam Kristof	Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections.	ED&TC	1997	DBLP DOI BibTeX RDF
25	Colin M. Maunder	A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
25	Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin	Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
24	Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan	ScanBist: A Multifrequency Scan-Based BIST Method.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
23	Dave Stang, Ramaswami Dandapani	An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.	ITC	2002	DBLP DOI BibTeX RDF
21	Jari Hannu, Markku Moilanen	Methods of Testing Discrete Semiconductors in the 1149.4 Environment.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	1149.4, Discrete semiconductors, Boundary scan
21	Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park	An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
21	Franc Novak, Anton Biasizzo	Security Extension for IEEE Std 1149.1.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	security, test, boundary-scan
21	Carl Jeffrey, Reuben Cutajar, Andrew Richardson 0001, Stephen Prosser, M. Lickess, Stephen Riches	The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	IEEE1149.4, IDR, fault tolerance, boundary scan, on-line monitoring
21	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou	Intrinsic response for analog module testing using an analog testability bus.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
21	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
21	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
21	Chauchin Su, Shyh-Jye Jou	Decentralized BIST Methodology for System Level Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, BIST, DFT, boundary scan
21	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
21	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang	Using a single input to support multiple scan chains.	ICCAD	1998	DBLP DOI BibTeX RDF	boundary scan (IEEE 1149.1) and test compaction, test generation, design for testability, scan based design
21	Joel A. Jorgenson, Russell J. Wagner	Design-For-Test in a Multiple Substrate Multichip Module.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	Multichip Module (MCM) Test, Known-Good Die (KGD), Ball Grid Array (BGA), Built-In-Self-Test (BIST), boundary-scan
21	Thomas M. Storey, Bruce McWilliam	A Test Methodology for High Performance MCMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing
21	Ken Posse	A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault diagnosis, Boundary-Scan, Multichip Module, MCM, interconnect testing, manufacturing defects
21	T. Haulin	Built-in parametric test for controlled impedance I/Os.	VTS	1997	DBLP DOI BibTeX RDF	controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
21	Johan Verfaillie, Didier Haspeslagh	A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	mixed-signal DFT, mixed-signal boundary scan, modular mixed-signal test
21	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
21	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan