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Publication years (Num. hits)
1974-1984 (20) 1985-1988 (26) 1989-1990 (19) 1991-1992 (20) 1993-1994 (30) 1995 (33) 1996 (29) 1997 (39) 1998 (20) 1999 (42) 2000 (53) 2001 (41) 2002 (49) 2003 (77) 2004 (87) 2005 (87) 2006 (100) 2007 (99) 2008 (70) 2009 (43) 2010 (27) 2011-2012 (21) 2013 (17) 2014 (16) 2015 (26) 2016 (25) 2017 (29) 2018 (22) 2019 (52) 2020 (44) 2021 (44) 2022 (42) 2023 (49) 2024 (9)
Publication types (Num. hits)
article(481) data(1) incollection(4) inproceedings(914) phdthesis(7)
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The graphs summarize 1178 occurrences of 716 keywords

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Found 1407 publication records. Showing 1407 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
107Susumu Matsumae, Nobuki Tokura Simulating a Mesh with Separable Buses by a Mesh with Partitioned Buses. Search on Bibsonomy ISPAN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF two-dimensional mesh-connected computer, mesh with separable buses, mesh with partitioned buses, broadcasting, propagation delay, simulation algorithm
89Susumu Matsumae Optimal Simulation of Meshes with Dynamically Separable Buses by Meshes with Statically Partitioned Buses. Search on Bibsonomy ISPAN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
89Susumu Matsumae Simulation of Meshes with Separable Buses by Meshes with Multiple Partitioned Buses. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
84Jeffrey A. Floyd, Matt Perry Real-time on-board bus testing. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds
82Kazuo Iwama, Eiji Miyano Oblivious Routing Algorithms on the Mesh of Buses. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
66Mounir Hamdi, J. Tong, C. W. Kin Fast sorting algorithms on reconfigurable array of processors with optical buses. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
66Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye An energy-efficient temporal encoding circuit technique for on-chip high performance buses. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF on-chip buses, energy-efficient, encoding, repeaters
66Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001 Semigroup and Prefix Computations on Improved Generalized Mesh-Connected Computers with Multiple Buses. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, bus, mesh-connected computer
65Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
58Jill H. Y. Law, Evangeline F. Y. Young Multi-bend bus driven floorplanning. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF bus planning, floorplanning, VLSI CAD
57Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar Energy-efficient encoding techniques for off-chip data buses. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low-power data buses, bus switching, internal capacitances, encoding
57Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif Approaches to run-time and standby mode leakage reduction in global buses. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF pulsed buses, leakage, repeaters, MTCMOS
57Jihong Ren, Mark R. Greenstreet Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF equalizing filters, optimal synthesis, crosstalk, buses
57Biing-Feng Wang, Stephan Olariu On the Power of the Mesh with Hybrid Buses. Search on Bibsonomy ISPAN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Mesh with Hybrid Buses, Mesh with Multiple Broadcasting, simulation, parallel algorithms, PRAM, reconfigurable mesh
57Zicheng Guo, Rami G. Melhem Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings
57Mauricio J. Serrano, Behrooz Parhami Optimal Architectures and Algorithms for Mesh-Connected Parallel Computers with Separable Row/Column Buses. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF mesh-connected, separable row and column buses, parallel algorithms, computational complexity, parallel computers, parallel architectures, time complexity, processing elements, data routing, two-dimensional mesh, prefix computation, semigroup computation
50Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-Il Park A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting. Search on Bibsonomy ICPP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Mesh with Buses, Parallel Computing, Multicast, Interconnection Network, Broadcast, Collective Communication
50Jongmin Lee, Eujoon Byun, Hanmook Park, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh CPS-SIM: configurable and accurate clock precision solid state drive simulator. Search on Bibsonomy SAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF SSD (solid state drive), clock precision SSD simulator, configurability, NAND flash memory, FTL (flash translation layer)
50Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong OPC-Friendly Bus Driven Floorplanning. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
50Marcello Coppola Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network. Search on Bibsonomy IOLTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Sotirios G. Ziavras Performance Analysis for an Important Class of Parallel-Processing Networks. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF complexity of algorithms, parallel algorithms, broadcasting, cost analysis, mesh architecture
50Cauligi S. Raghavendra HMESH: A VLSI Architecture for Parallel Processing. Search on Bibsonomy CONPAR The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
50Sanguthevar Rajasekaran Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mesh with reconfigurable buses, mesh with fixed buses, k?k routing, k?k sorting, parallel computing, randomized algorithms, sorting, mesh, packet routing, Reconfigurable networks
50Kuo-Liang Chung, Yu-Chih Lin A Parametric Algorithm for Semigroup Computation on Mesh with Buses. Search on Bibsonomy Computing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mesh-connected computers with segmented buses, reconfigurable buses, parametric parallel algorithm, broadcasting, Semigroup computation
49Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang Frequent value encoding for low power data buses. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
49Maged Ghoneima, Yehea I. Ismail Optimum positioning of interleaved repeaters In bidirectional buses. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF delay, interconnect, noise, repeaters, buses
49Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan Odd/even bus invert with two-phase transfer for buses with coupling. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF bus invert, buses with coupling, coding for low-power I/O
49Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001 An Improved Generalization of Mesh-Connected Computers with Multiple Buses. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, Bus, mesh-connected computer
49Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems
49Sharath Jayaprakash, Nihar R. Mahapatra Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Krishnan Sundaresan, Nihar R. Mahapatra An Accurate Energy and Thermal Model for Global Signal Buses. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller 0001 Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne H. Wolf A dictionary-based en/decoding scheme for low-power data buses. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
49Amos Beimel, Shlomi Dolev Buses for Anonymous Message Delivery. Search on Bibsonomy J. Cryptol. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Privacy, Traffic analysis, Anonymous communication
49William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano Power optimization of system-level address buses based on software profiling. Search on Bibsonomy CODES The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen ESD buses for whole-chip ESD protection. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
49Sanguthevar Rajasekaran Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing, Sorting, and Selection. Search on Bibsonomy ESA The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
42Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu A comprehensive estimation technique for high-level synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
42Mircea R. Stan, Wayne P. Burleson Coding a terminated bus for low power. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
41Anu G. Bourgeois, Jerry L. Trahan Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Reconfigurable models, optical buses, complexity, model simulations
41Sandy Pavel, Selim G. Akl Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses. Search on Bibsonomy IPPS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF arrays with reconfigurable optical buses, Hough transform
41Mounir Hamdi, Yi Pan 0001 Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
41Jop F. Sibeyn, Michael Kaufmann 0001, Rajeev Raman Randomized Routing on Meshes with Buses. Search on Bibsonomy ESA The full citation details ... 1993 DBLP  DOI  BibTeX  RDF algorithms, parallel computation, lower bounds, meshes, randomization, coloring, packet routing, buses
40Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie 0001 Delay and Energy Efficient Data Transmission for On-Chip Buses. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Krishnan Sundaresan, Nihar R. Mahapatra Value-based bit ordering for energy optimization of on-chip global signal buses. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Boon-Chong Seet, Chiew Tong Lau, Wen-Jing Hsu, Bu-Sung Lee A Mobile System of Super-Peers Using City Buses. Search on Bibsonomy PerCom Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon Driver pre-emphasis techniques for on-chip global buses. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
40Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar A tunable bus encoder for off-chip data buses. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF TUBE, data bus, data bus encoding, tunable bus encoder
40Yi Zhao, Sujit Dey, Li Chen Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Jiangjiang Liu 0002, Nihar R. Mahapatra, Krishnan Sundaresan Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. Search on Bibsonomy HiPC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Susumu Matsumae An Efficient Scaling-Simulation Algorithm of Reconfigurable Meshes by Meshes with Partitioned Buses. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan Power efficient encoding techniques for off-chip data buses. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FV, FV-MSB-LSB, data bus, low power, bus encoding
40Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
40Yi Zhao, Li Chen, Sujit Dey On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Kazuo Iwama, Eiji Miyano, Satoshi Tajima, Hisao Tamaki Efficient Randomized Routing Algorithms on the Two-Dimensional Mesh of Buses. Search on Bibsonomy COCOON The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
40Ville Leppänen Embedding and Emulation Results for Static Multichannel Mesh of Optical Buses. Search on Bibsonomy Euro-Par The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
40Kuo-Liang Chung Prefix Computations on a Generalized Mesh-Connected Computer with Multiple Buses. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
40Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
40Kazuo Iwama, Eiji Miyano Routing Problems on the Mesh of Buses. Search on Bibsonomy ISAAC The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
34Andrew Tjang, Michael Pagliorola, Hiral Patel, Xiaoyan Li, Richard P. Martin Active Tapes: Bus-Based Sensor Networks. Search on Bibsonomy LCN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Power buses, Data buses, Sensor networks
34Russ Miller, Quentin F. Stout Simulating Essential Pyramids. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF essential pyramids, pyramid algorithms, mesh with row and column buses, mesh with reconfigurable buses, pyramid computer, simulation, image processing, parallel processing, virtual machines, hypercube, mesh, computerised picture processing, optimal algorithms, PRAM, mesh-of-trees
34Masaru Takesue Psi-Cubes: Recursive Bused Fat-Hypercubes for Multilevel Snoopy Caches. Search on Bibsonomy ISPAN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Bused networks, recursive networks, trees of buses, multilevel caches, coherence directories, clustering, Hamming codes
33Tilen Ma, Evangeline F. Y. Young TCG-based multi-bend bus driven floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Xiaolan Zhang 0003, Jim Kurose, Brian Neil Levine, Donald F. Towsley, Honggang Zhang 0003 Study of a bus-based disruption-tolerant network: mobility modeling and impact on routing. Search on Bibsonomy MobiCom The full citation details ... 2007 DBLP  DOI  BibTeX  RDF mobility trace modeling, DTN, epidemic routing
33Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Sujan Pandey, Manfred Glesner Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF communication bus synthesis, voltage scaling
33Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt Adaptive low-power address encoding techniques using self-organizing lists. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Makoto Sugihara, Hiroto Yasuura Optimization of Test Accesses with a Combined BIST and External Test Scheme. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
33Chittaranjan A. Mandal, R. M. Zimmer A Genetic Algorithm for the Synthesis of Structured Data Paths. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation
33Friedhelm Meyer auf der Heide, Harald Räcke, Matthias Westermann Data management in hierarchical bus networks. Search on Bibsonomy SPAA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Aurobindo Dasgupta, Ramesh Karri High-reliability, low-energy microarchitecture synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Scott T. Leutenegger, Mary K. Vernon A Mean-Value Performance Analysis of a New Multiprocessor Architecture. Search on Bibsonomy SIGMETRICS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
33Kimish Patel, Wonbok Lee, Massoud Pedram In-order pulsed charge recycling in off-chip data buses. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF data buses, power, charge recycling
33Maged Ghoneima, Yehea I. Ismail Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF low power, interconnects, buses, coupling capacitance
33Michel Dubois 0001 Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF shared interleaved memory, cache-based multiprocessors, general-purpose computing, dynamic instruction mix statistics, performance evaluation, performance, throughput, multiprocessing systems, buffer storage, multitasking, private cache, multiple buses
32Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Tomoya Kitani, Takashi Shinkawa, Naoki Shibata, Keiichi Yasumoto, Minoru Ito, Teruo Higashino Efficient VANET-Based Traffic Information Sharing using Buses on Regular Routes. Search on Bibsonomy VTC Spring The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Michel Sede, Xu Li 0009, Da Li, Min-You Wu, Minglu Li 0001, Wei Shu Routing in Large-Scale Buses Ad Hoc Networks. Search on Bibsonomy WCNC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Dirk Koch, Christian Haubelt, Jürgen Teich Efficient Reconfigurable On-Chip Buses for FPGAs. Search on Bibsonomy FCCM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Karthik Duraisami, Enrico Macii, Massimo Poncino Energy efficiency bounds of pulse-encoded buses. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF power reduction., pulse wave transmission, high-speed interconnect, transition activity
32Krishnan Sundaresan, Nihar R. Mahapatra Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
32David C. Keezer, Dany Minier, Patrice Ducharme Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
32Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor Physical design implementation of segmented buses to reduce communication energy. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling Optimal memoryless encoding for low power off-chip data buses. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri Memory-based crosstalk canceling CODECs for on-chip buses. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF address bus, low power, encoding, energy dissipation
32Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen Language-Based High Level Transaction Extraction on On-chip Buses. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Maged Ghoneima, Yehea I. Ismail Optimum positioning of interleaved repeaters in bidirectional buses. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura A variation-aware low-power coding methodology for tightly coupled buses. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Teck Meng Lim, Boon-Chong Seet, Bu-Sung Lee, Chai Kiat Yeo, Andreas Kassler Pervasive Communication for Commuters in Public Buses. Search on Bibsonomy PerCom Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang 0002 VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Maged Ghoneima, Yehea I. Ismail Accurate decoupling of capacitively coupled buses. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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