Search results for "CGRA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
108	Yoonjin Kim, Rabi N. Mahapatra	Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.	DAC	2009	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems
97	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
97	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek	SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
78	Yoonjin Kim, Rabi N. Mahapatra	A New Array Fabric for Coarse-Grained Reconfigurable Architecture.	DSD	2008	DBLP DOI BibTeX RDF
78	Song Li-Guo, Jiang Yu-Xian	A Route System Based on Ant Colony for Coarse-Grain Reconfigurable Architecture.	ICNC (2)	2006	DBLP DOI BibTeX RDF
60	Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke	CGRA express: accelerating execution using dynamic operation fusion.	CASES	2009	DBLP DOI BibTeX RDF	latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture
58	Yoonjin Kim, Rabi N. Mahapatra	Dynamic context management for low power coarse-grained reconfigurable architecture.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	context word, embedded systems, system-on-chip (soc), digital signal processing, coarse-grained reconfigurable architecture, configuration cache
58	Yan Guo, Sanyou Zeng, Lishan Kang, Gang Liu, Nannan Hu, Kuo Zhao	A Route System Based on Genetic Algorithm for Coarse-Grain Reconfigurable Architecture.	ISICA	2009	DBLP DOI BibTeX RDF	resources-constrained multi-pair shortest path problem in directed graphs, Multi-pair path encoding, Genetic algorithm, Coarse-grain reconfigurable architecture
58	Yoonjin Kim, Rabi N. Mahapatra	Dynamically compressible context architecture for low power coarse-grained reconfigurable array.	ICCD	2007	DBLP DOI BibTeX RDF
58	Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001	QUKU: A Two-Level Reconfigurable Architecture.	ISVLSI	2006	DBLP DOI BibTeX RDF
58	Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001	QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection.	ARC	2006	DBLP DOI BibTeX RDF
57	Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula	Enabling Multithreading on CGRAs.	ICPP	2011	DBLP DOI BibTeX RDF	CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
43	Rong Zhu, Bo Wang, Dajiang Liu	RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains.	DATE	2022	DBLP DOI BibTeX RDF
43	Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang 0003, Tianyi Yu	CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper).	ASAP	2021	DBLP DOI BibTeX RDF
43	S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson	CGRA-ME: A unified framework for CGRA modelling and exploration.	ASAP	2017	DBLP DOI BibTeX RDF
39	Taewook Oh, Bernhard Egger 0002, Hyunchul Park 0001, Scott A. Mahlke	Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.	LCTES	2009	DBLP DOI BibTeX RDF	software pipelining, placement and routing, coarse-grained reconfigurable architectures
39	Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.	DATE	2008	DBLP DOI BibTeX RDF
39	Yoonjin Kim, Rabi N. Mahapatra	Reusable context pipelining for low power coarse-grained reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
39	Thomas Lenart, Henrik Svensson, Viktor Öwall	Modeling and exploration of a reconfigurable architecture for digital holographic imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
39	Hyunchul Park 0001, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
28	Leipo Yan, Thambipillai Srikanthan, Niu Gang	Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures.	LCTES	2006	DBLP DOI BibTeX RDF	CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation
28	Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek	Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.	ISLPED	2006	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping
21	Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang	HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
21	Dan Wu, Peng Chen 0027, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra	Flip: Data-centric Edge CGRA Accelerator.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
21	Dajiang Liu, Yuxin Xia, Jiaxing Shang, Jiang Zhong, Peng Ouyang, Shouyi Yin	E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping.	HPCA	2024	DBLP DOI BibTeX RDF
21	Chen Yin, Naifeng Jing, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao	A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
21	Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin	TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
21	Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy	An Efficient and Flexible Stochastic CGRA Mapping Approach.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
21	Reza Kazerooni-Zand, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
21	Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu 0001, Leibo Liu, Shaojun Wei, Shouyi Yin	WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow.	CoRR	2023	DBLP DOI BibTeX RDF
21	Dan Wu, Peng Chen 0027, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra	Flip: Data-Centric Edge CGRA Accelerator.	CoRR	2023	DBLP DOI BibTeX RDF
21	Hans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi	Generating CGRA Processing Element Hardware with CGRAgen.	DSD	2023	DBLP DOI BibTeX RDF
21	Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima	Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission.	MCSoC	2023	DBLP DOI BibTeX RDF
21	Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson	GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.	FPL	2023	DBLP DOI BibTeX RDF
21	Rui Rodrigues de Mello Junior, Gabriel Antoine Louis Paillard, Leandro Santiago de Araújo, Pedro C. Diniz, Felipe M. G. França	GSink - A Runtime for Gamma Programs and its CGRA Mapping Proposal.	IPDPS Workshops	2023	DBLP DOI BibTeX RDF
21	Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano	Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC.	IPDPS Workshops	2023	DBLP DOI BibTeX RDF
21	Omar Ragheb, Rami Beidas, Jason Helge Anderson	Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility.	IPDPS Workshops	2023	DBLP DOI BibTeX RDF
21	Yuan Dai, Yunhui Qiu, Qilong Zhu, Jingyuan Li, Wenbo Yin, Lingli Wang	UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization.	FCCM	2023	DBLP DOI BibTeX RDF
21	Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima	Efficient and High-Speed CGRA Accelerator for Cryptographic Applications.	candar	2023	DBLP DOI BibTeX RDF
21	Cheng Tan 0002, Deepak Patil, Antonino Tumeo, Gabriel Weisz, Steven K. Reinhardt, Jeff Zhang 0001	VecPAC: A Vectorizable and Precision-Aware CGRA.	ICCAD	2023	DBLP DOI BibTeX RDF
21	Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh	FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.	ICCAD	2023	DBLP DOI BibTeX RDF
21	Tomoya Akabe, Ryotaro Funai, Yasuhiko Nakashima	Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA.	NEWCAS	2023	DBLP DOI BibTeX RDF
21	Felix Böseler, Jörg Walter 0001	A Flexible Graph Language for a Model-Based Semi-Automatic CGRA Compilation Flow.	FDL	2023	DBLP DOI BibTeX RDF
21	Jiangnan Li, Chang Cai, Yaya Zhao, Yazhou Yan, Wenbo Yin, Lingli Wang	GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping.	ICFPT	2023	DBLP DOI BibTeX RDF
21	Qilong Zhu, Yuhang Cao, Yunhui Qiu, Xuchen Gao, Wenbo Yin, Lingli Wang	A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.	ICFPT	2023	DBLP DOI BibTeX RDF
21	Tobias Kaiser, Friedel Gerfers	A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
21	Jingyuan Li, Yunhui Qiu, Guowei Zhu, Qilong Zhu, Wenbo Yin, Lingli Wang	THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE.	ISCAS	2023	DBLP DOI BibTeX RDF
21	Mingyang Chen, Yunhui Qiu, Kaixiang Zhu, Lingli Wang	An Automatic Optimization Method of Combinational Logic Loops in CGRA.	ASICON	2023	DBLP DOI BibTeX RDF
21	Dajiang Liu, Di Mou, Rong Zhu, Yan Zhuang, Jiaxing Shang, Jiang Zhong, Shouyi Yin	DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs.	DAC	2023	DBLP DOI BibTeX RDF
21	Yixuan Luo, Cheng Tan 0002, Nicolas Bohm Agostini, Ang Li 0006, Antonino Tumeo, Nirav Dave, Tong Geng	ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs.	DAC	2023	DBLP DOI BibTeX RDF
21	Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu 0001, Leibo Liu, Shaojun Wei, Shouyi Yin	RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.	DAC	2023	DBLP DOI BibTeX RDF
21	Liao Huang, Dajiang Liu	Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations.	DAC	2023	DBLP DOI BibTeX RDF
21	Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele	HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
21	Baofen Yuan, Jianfeng Zhu 0001, Xingchen Man, Zijiao Ma, Shouyi Yin, Shaojun Wei, Leibo Liu	Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
21	Zhaoying Li, Dhananjaya Wijerathne, Xianzhang Chen, Anuj Pathania, Tulika Mitra	ChordMap: Automated Mapping of Streaming Applications Onto CGRA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
21	Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci	Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators.	PRIME	2022	DBLP DOI BibTeX RDF
21	Tobias Kaiser, Friedel Gerfers	Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA.	ARCS	2022	DBLP DOI BibTeX RDF
21	Rami Beidas, Jason Helge Anderson	CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams.	ASP-DAC	2022	DBLP DOI BibTeX RDF
21	Kevin J. M. Martin	Twenty Years of Automated Methods for Mapping Applications on CGRA.	IPDPS Workshops	2022	DBLP DOI BibTeX RDF
21	Ilan Tayari	CGRA4HPC 2022 Invited Speaker: Practical, scalable, and easy-to-use CGRA for HPC.	IPDPS Workshops	2022	DBLP DOI BibTeX RDF
21	Takuya Kojima, Boma A. Adhi, Carlos Cortes, Yiyu Tan, Kentaro Sano	An Architecture- Independent CGRA Compiler enabling OpenMP Applications.	IPDPS Workshops	2022	DBLP DOI BibTeX RDF
21	Yan Zhuang, Zhihao Zhang, Dajiang Liu	Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning.	ICCAD	2022	DBLP DOI BibTeX RDF
21	Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano	Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage.	FPT	2022	DBLP DOI BibTeX RDF
21	Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano	Body Bias Control on a CGRA based on Convex Optimization.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
21	Lei Dai, Ying Wang 0001, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li	Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance.	ICCD	2022	DBLP DOI BibTeX RDF
21	Long Tan, Mingyu Yan, Duo Wang, Wenming Li, Xiaochun Ye, Dongrui Fan	MatGraph: An Energy-Efficient and Flexible CGRA Engine for Matrix-Based Graph Analytics.	ICA3PP	2022	DBLP DOI BibTeX RDF
21	Long Tan, Mingyu Yan, Xiaochun Ye, Dongrui Fan	HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
21	Nikhil Sambhus, Tarek S. Abdelrahman	Reuse-Aware Partitioning of Dataflow Graphs on a Tightly-Coupled CGRA.	ISPA/BDCloud/SocialCom/SustainCom	2022	DBLP DOI BibTeX RDF
21	Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh	REVAMP: a systematic framework for heterogeneous CGRA realization.	ASPLOS	2022	DBLP DOI BibTeX RDF
21	Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao	GEML: GNN-based efficient mapping method for large loop applications on CGRA.	DAC	2022	DBLP DOI BibTeX RDF
21	Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra	PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA.	DAC	2022	DBLP DOI BibTeX RDF
21	Mark Wijtvliet, Henk Corporaal, Akash Kumar 0001	CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures.	ACM Trans. Reconfigurable Technol. Syst.	2021	DBLP DOI BibTeX RDF
21	Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Clark W. Barrett, Mark Horowitz, Pat Hanrahan, Priyanka Raina	Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis.	CoRR	2021	DBLP BibTeX RDF
21	Dennis Wolf 0001, Andreas Engel 0003, Tajas Ruschke, Andreas Koch 0001, Christian Hochberger	UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment.	J. Signal Process. Syst.	2021	DBLP DOI BibTeX RDF
21	Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Philippe Coussy	Floating Point CGRA based Ultra-Low Power DSP Accelerator.	J. Signal Process. Syst.	2021	DBLP DOI BibTeX RDF
21	Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele	HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.	DATE	2021	DBLP DOI BibTeX RDF
21	Chen Yin, Qin Wang 0009, Jianfei Jiang 0001, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing	Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.	DATE	2021	DBLP DOI BibTeX RDF
21	Jungi Lee, Jongeun Lee	NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks.	DATE	2021	DBLP DOI BibTeX RDF
21	Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems.	DSD	2021	DBLP DOI BibTeX RDF
21	Ramon Wirsch, Christian Hochberger	Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.	ARCS	2021	DBLP DOI BibTeX RDF
21	Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy	Hardware Based Loop Optimization for CGRA Architectures.	ARC	2021	DBLP DOI BibTeX RDF
21	Aleksandr Penskoi	Synthesis Method for CGRA Processors based on Imitation Model.	MECO	2021	DBLP DOI BibTeX RDF
21	Zahra Ebrahimi, Akash Kumar 0001	BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge.	ISCAS	2021	DBLP DOI BibTeX RDF
21	Maria D. Vieira, Michael Canesche, Lucas Bragança, Josué Campos, Mateus Silva, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif	RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays.	ISCAS	2021	DBLP DOI BibTeX RDF
21	Graham Gobieski, Ahmet Oguz Atli, Kenneth Mai, Brandon Lucia, Nathan Beckmann	Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture.	ISCA	2021	DBLP DOI BibTeX RDF
21	Jinho Lee, Trevor E. Carlson	Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs.	DAC	2021	DBLP DOI BibTeX RDF
21	Yijiang Guo, Jiarui Wang, Jiaxi Zhang 0001, Guojie Luo	Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping.	DAC	2021	DBLP DOI BibTeX RDF
21	Guiqiang Peng, Leibo Liu, Sheng Zhou 0001, Shouyi Yin, Shaojun Wei	A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
21	Jiang Sha, Wenbo Song, Yu Gong, Yingying Zhao	Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method.	IEEE Access	2020	DBLP DOI BibTeX RDF
21	Zhongyuan Zhao 0004, Weiguang Sheng, Qin Wang 0009, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao	Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
21	Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique 0001	X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
21	Wei Ge, Shenghua Chen, Benyu Liu, Min Zhu 0001, Bo Liu 0019	A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA.	IEICE Trans. Inf. Syst.	2020	DBLP DOI BibTeX RDF
21	Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy	Energy Efficient Acceleration Of Floating Point Applications Onto CGRA.	ICASSP	2020	DBLP DOI BibTeX RDF
21	Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner 0001, Mateus Beck Rutzig, Antonio Carlos Schneider Beck	MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge.	FPL	2020	DBLP DOI BibTeX RDF
21	George Charitopoulos, Dionisios N. Pnevmatikatos	A CGRA Definition Framework for Dataflow Applications.	ARC	2020	DBLP DOI BibTeX RDF
21	Tong Geng, Chunshu Wu, Cheng Tan 0002, Bo Fang, Ang Li 0006, Martin C. Herbordt	CQNN: a CGRA-based QNN Framework.	HPEC	2020	DBLP DOI BibTeX RDF
21	Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin	TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.	DAC	2020	DBLP DOI BibTeX RDF
21	Loris Duch, Soumya Basu 0002, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza	i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.	IEEE Embed. Syst. Lett.	2019	DBLP DOI BibTeX RDF
21	Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001	R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
21	Dajiang Liu, Shouyi Yin, Guojie Luo, Jiaxing Shang, Leibo Liu, Shaojun Wei, Yong Feng 0002, Shangbo Zhou	Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF