Search results for "Design-for-Debug"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Shan Tang, Qiang Xu 0001	A multi-core debug platform for NoC-based systems.	DATE	2007	DBLP DOI BibTeX RDF
79	Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers	Design-For-Debug in Hardware/Software Co-Design.	CODES	1997	DBLP DOI BibTeX RDF	system integration and test, hardware/software co-design, design validation, design-for-debug
62	Shan Tang, Qiang Xu 0001	In-band Cross-Trigger Event Transmission for Transaction-Based Debug.	DATE	2008	DBLP DOI BibTeX RDF
54	Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller	A reconfigurable design-for-debug infrastructure for SoCs.	DAC	2006	DBLP DOI BibTeX RDF	assertion-based debug, at-speed debug, what-if experiments, silicon debug
54	Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger	Silicon Symptoms to Solutions: Applying Design for Debug Techniques.	ITC	2002	DBLP DOI BibTeX RDF
46	Bart Vermeulen	Functional Debug Techniques for Embedded Systems.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
40	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
38	Yiorgos Makris, Alex Orailoglu	A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.	DFT	1999	DBLP DOI BibTeX RDF
36	Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang	Visibility enhancement for silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	silicon validation, functional verification, silicon debug
20	Bart Vermeulen, Sandeep Kumar Goel	Design for Debug: Catching Design Errors in Digital Chips.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
20	Gustavo R. Alves, José Manuel Martins Ferreira	From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1.	VTS	1999	DBLP DOI BibTeX RDF
19	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
19	Bart Vermeulen, Kees Goossens, Siddharth Umrani	Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	communication-centric debug, debug, network-on-chip, design for debug
19	Sung-Boem Park, Subhasish Mitra	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.	DAC	2008	DBLP DOI BibTeX RDF	verification, debug, validation, design for debug
19	Ming-Chang Hsieh, Chih-Tsun Huang	An embedded infrastructure of debug and trace interface for the DSP platform.	DAC	2008	DBLP DOI BibTeX RDF	embedded debug and trace, compression, embedded processors, digital signal processors, design for debug
19	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	Diagnosing Silicon Failures Based on Functional Test Patterns.	MTV	2006	DBLP DOI BibTeX RDF	fault diagnosis, Silicon debug, design for debug
19	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel	Automatic generation of breakpoint hardware for silicon debug.	DAC	2004	DBLP DOI BibTeX RDF	hardware-breakpoints, design-flow, silicon-debug, design-for-debug
19	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
19	Bart Vermeulen, Tom Waayers, Sjaak Bakker	Multi-TAP Controller Architecture for Digital System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP
19	Harald P. E. Vranken	Debug Facilities in the TriMedia CPU64 Architecture.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	application debug, VLIW processor, design-for-debug
19	Jayabrata Ghosh-Dastidar, Nur A. Touba	A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains.	VTS	2000	DBLP DOI BibTeX RDF	built-in self-test Scan Chains, Design-for-Diagnosis, Multi-Input Signature Register, Design-for-Testability, LFSR, Integrated Circuits, Integrated Circuits, Digital Testing, Design-for-Debug
18	Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli	DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring.	DAC	2019	DBLP DOI BibTeX RDF
18	Sabyasachi Deyati	Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.		2017	RDF
18	Abhishek Basak, Swarup Bhunia, Sandip Ray	Exploiting design-for-debug for flexible SoC security architecture.	DAC	2016	DBLP DOI BibTeX RDF
18	Jerry Backer, David Hély, Ramesh Karri	Secure design-for-debug for Systems-on-Chip.	ITC	2015	DBLP DOI BibTeX RDF
18	Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen	Design-for-debug routing for FIB probing.	DATE	2014	DBLP DOI BibTeX RDF
18	John Giacobbe	Physical design for debug: insurance policy for IC's.	ISPD	2013	DBLP DOI BibTeX RDF
18	Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici	Design-for-Debug Architecture for Distributed Embedded Logic Analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
18	Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen	Design-for-debug layout adjustment for FIB probing and circuit editing.	ITC	2011	DBLP DOI BibTeX RDF
18	Nicola Nicolici, Ho Fai Ko	Design-for-debug for post-silicon validation: Can high-level descriptions help?	HLDVT	2009	DBLP DOI BibTeX RDF
18	Hyunbean Yi, Sungju Park, Sandip Kundu	A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC.	ATS	2008	DBLP DOI BibTeX RDF
18	Prawat Nagvajara, Baris Taskin	Design-for-Debug: A Vital Aspect in Education.	MSE	2007	DBLP DOI BibTeX RDF
18	Hong Hao, Rick Avra	Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation.	ITC	1995	DBLP DOI BibTeX RDF
18	Young-Jun Kwon, Ben Mathew, Hong Hao	FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.	ITC	1998	DBLP DOI BibTeX RDF
11	Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park	An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
11	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	David Castells-Rufas, Jordi Carrabina	Jumble: A Hardware-in-the-Loop Simulation System for JHDL.	FCCM	2007	DBLP DOI BibTeX RDF