Search results for "Diminished-1"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Haridimos T. Vergos, Costas Efstathiou	Diminished-1 Modulo 2n + 1 Squarer Design.	DSD	2004	DBLP DOI BibTeX RDF
47	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient Diminished-1 Modulo 2^n+1 Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
43	Kooroush Manochehri, Saadat Pourmozafari, Babak Sadeghiyan	Efficient Methods in Converting to Modulo 2^n+1 and 2^n-1.	ITNG	2006	DBLP DOI BibTeX RDF	Diminished-1, RNS, Modular multiplication, CSA, Wallace tree
35	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
25	Zhongde Wang, Graham A. Jullien, William C. Miller	An efficient tree architecture for modulo 2n+1 multiplication.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
22	Ghassem Jaberipur, Dariush Badri, Jeong-A Lee	A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
22	Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos	On the Diminished-1 Modulo 2n+1 Addition and Subtraction.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
22	Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena	Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
22	Ghassem Jaberipur, Armin Belghadr, Saeed Nejati	Impact of diminished-1 encoding on residue number systems arithmetic units and converters.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
22	Ghassem Jaberipur, Armin Belghadr	(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling.	Comput. Electr. Eng.	2017	DBLP DOI BibTeX RDF
22	Xiaolan Lv, Ruohe Yao	Efficient diminished-1 modulo 2n+1 multiplier architectures.	IJCNN	2014	DBLP DOI BibTeX RDF
22	Dragana Zivaljevic, Negovan Stamenkovic, Vidosav Stojanovic	Digital filter implementation based on the RNS with diminished-1 encoded channel.	TSP	2012	DBLP DOI BibTeX RDF
22	Jian Wen Chen, Ruo He Yao	Efficient modulo 2n + 1 multipliers for diminished-1 representation.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
22	Haridimos T. Vergos, Costas Efstathiou	A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
22	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient modulo 2n+1 tree multipliers for diminished-1 operands.	ICECS	2003	DBLP DOI BibTeX RDF
13	Tuukka Toivonen, Janne Heikkilä	Video filtering with Fermat number theoretic transforms using residue number system.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF