Search results for "FPGA-synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Wen-Jong Fang, Allen C.-H. Wu	Multiway FPGA partitioning by fully exploiting design hierarchy.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis
56	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
46	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
46	Jason Cong, Kirill Minkovich	Optimality study of logic synthesis for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
31	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
30	TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang	Logic synthesis for field-programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
30	Lei Cheng 0001, Deming Chen, Martin D. F. Wong	DDBDD: Delay-Driven BDD Synthesis for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
30	Lei Cheng 0001, Deming Chen, Martin D. F. Wong	DDBDD: Delay-Driven BDD Synthesis for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
27	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	LUT-Based FPGA Technology Mapping, Area/Performance Trade-Off and Timing Driven FPGA Synthesis
24	Wen-Jong Fang, Allen C.-H. Wu	Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy.	DAC	1997	DBLP DOI BibTeX RDF
20	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.	DAC	2008	DBLP DOI BibTeX RDF	BCP, FPGA, reconfigurable, SAT solver, co-processor
18	Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil	Parameterized Looped Schedules for Compact Representationof Execution Sequences.	ASAP	2006	DBLP DOI BibTeX RDF
18	Francisco-Javier Veredas, Jordi Carrabina	Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.	PATMOS	2005	DBLP DOI BibTeX RDF
17	Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry.	DATE	2023	DBLP DOI BibTeX RDF
16	Christophe Desmouliers, Erdal Oruklu, Jafar Saniie	FPGA-based design of a high-performance and modular video processing platform.	EIT	2009	DBLP DOI BibTeX RDF
16	Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada	Compact Spiking Neural Network Implementation in FPGA.	FPL	2000	DBLP DOI BibTeX RDF
16	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
16	Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi	An improved synthesis method for low power hardwired FIR filters.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA synthesis, parallel FIR filter, power-of-two, common subexpression elimination
16	Jason Cong, Yizhou Lin, Wangning Long	SPFD-based global rewiring.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis
16	Kang Yi, Seong Yong Ohm	A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping.	ICCD	1999	DBLP DOI BibTeX RDF	Cell Matching, FPGA Technology Mapping, FPGA Synthesis
16	Wen-Jong Fang, Allen C.-H. Wu	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations.	ICCAD	1996	DBLP DOI BibTeX RDF	Multiple-FPGA partitioning, multiple-FPGA synthesis, functional structuring and functional partitioning
15	Iyad Ouaiss, Ranga Vemuri	Efficient Resource Arbitration in Reconfigurable Computing Environments.	DATE	2000	DBLP DOI BibTeX RDF
14	Chun Zhang, Yu Hu 0002, Lingli Wang, Lei He 0001, Jiarong Tong	Building a faster boolean matcher using bloom filter.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, SAT, bloom filter, boolean matching, re-synthesis
14	Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi	A VHDL Generation Tool for Optimized Parallel FIR Filters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
14	Jirong Liao, Weng-Fai Wong, Tulika Mitra	A Model for Hardware Realization of Kernel Loops.	FPL	2003	DBLP DOI BibTeX RDF
12	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen	ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert Ho-Ching Iu, Sung-Mo Steve Kang 0001, Jason Kamran Eshraghian	FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
12	Federico Rossi 0003, Lorenzo Fiaschi, Marco Cococcioni, Sergio Saponara	Design and FPGA Synthesis of BAN Processing Unit for Non-Archimedean Number Crunching.	ApplePies	2022	DBLP DOI BibTeX RDF
12	Ompal, Vishnu Mohan Mishra, Adesh Kumar	Zigbee Internode Communication and FPGA Synthesis Using Mesh, Star and Cluster Tree Topological Chip.	Wirel. Pers. Commun.	2021	DBLP DOI BibTeX RDF
12	Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert H. C. Iu, Jason Kamran Eshraghian, Sung Mo Kang 0001	FPGA Synthesis of Ternary Memristor-CMOS Decoders.	CoRR	2021	DBLP BibTeX RDF
12	Yann Herklotz, John Wickerson	Finding and Understanding Bugs in FPGA Synthesis Tools.	FPGA	2020	DBLP DOI BibTeX RDF
12	Adesh Kumar, Gaurav Verma, Mukul Kumar Gupta, Mohammad Salauddin, B. Khaleelu Rehman, Deepak Kumar 0009	3D Multilayer Mesh NoC Communication and FPGA Synthesis.	Wirel. Pers. Commun.	2019	DBLP DOI BibTeX RDF
12	Ehsan Jokar, Hadis Abolfathi, Arash Ahmadi, Majid Ahmadi	An Efficient Uniform-Segmented Neuron Model for Large-Scale Neuromorphic Circuit Design: Simulation and FPGA Synthesis Results.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Archit Gajjar, Xiaokun Yang, Lei Wu, Hakduran Koc, Ishaq Unwala, Yunxiang Zhang 0001, Yi Feng	An FPGA Synthesis of Face Detection Algorithm using HAAR Classifier.	ICACS	2018	DBLP DOI BibTeX RDF
12	Hamid Soleimani, Emmanuel M. Drakakis	A Compact Synchronous Cellular Model of Nonlinear Calcium Dynamics: Simulation and FPGA Synthesis Results.	IEEE Trans. Biomed. Circuits Syst.	2017	DBLP DOI BibTeX RDF
12	Swathi T. Gurumani, Jacob Tolar, Yao Chen 0008, Yun Liang 0001, Kyle Rupnow, Deming Chen	Integrated CUDA-to-FPGA Synthesis with Network-on-Chip.	FCCM	2014	DBLP DOI BibTeX RDF
12	Mohamed Azim Mohamed	FPGA Synthesis of VHDL OFDM System.	Wirel. Pers. Commun.	2013	DBLP DOI BibTeX RDF
12	Matthew Milford, John McAllister	Automatic FPGA synthesis of memory intensive C-based kernels.	ICSAMOS	2012	DBLP DOI BibTeX RDF
12	Arkadiusz Bukowiec, Piotr Mroz	An FPGA synthesis of the distributed control systems designed with Petri nets.	NESEA	2012	DBLP DOI BibTeX RDF
12	Mike Hutton, Vaughn Betz	FPGA Synthesis and Physical Design.	Embedded Systems Design and Verification	2009	DBLP DOI BibTeX RDF
12	Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus, Konstantin Tarletski	FSM decomposition with application to FPGA synthesis.	CompSysTech	2009	DBLP DOI BibTeX RDF
12	Yue Zhuo, Hao Li, Qiang Zhou 0001, Yici Cai, Xianlong Hong	New timing and routability driven placement algorithms for FPGA synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	congestion driven placement, physical synthesis, timing driven placement, net weight
12	Yue Zhuo, Hao Li, Saraju P. Mohanty	A Congestion Driven Placement Algorithm for FPGA Synthesis.	FPL	2006	DBLP DOI BibTeX RDF
12	Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius	Highly Automated FPGA Synthesis of Application-Specific Protocol Processors.	FPL	2005	DBLP DOI BibTeX RDF
12	Lech Józwiak, Artur Chojnacki	Effective and efficient FPGA synthesis through general functional decomposition.	J. Syst. Archit.	2003	DBLP DOI BibTeX RDF
12	Seong Yong Ohm, Ki-Yeol Ryu, Kang Yi	Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
12	Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo	A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.	FPL	2002	DBLP DOI BibTeX RDF
12	Christoph Scholl 0001	Functional decomposition with applications to FPGA synthesis.		2001	RDF
12	Lech Józwiak, Artur Chojnacki	Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures.	DSD	2001	DBLP DOI BibTeX RDF
12	Jian Qiao, Makoto Ikeda, Kunihiro Asada	Finding an optimal functional decomposition for LUT-based FPGA synthesis.	ASP-DAC	2001	DBLP DOI BibTeX RDF
12	Jian Qiao, Makoto Ikeda, Kunihiro Asada	Optimum Functional Decomposition for LUT-Based FPGA Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
12	John McCluskey	Practical Applications of Recursive VHDL Components in FPGA Synthesis.	FPGA	1999	DBLP DOI BibTeX RDF
12	Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu	A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	Per Lindgren, Rolf Drechsler, Bernd Becker 0001	Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.	ISMVL	1998	DBLP DOI BibTeX RDF
12	Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang	Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.	DAC	1998	DBLP DOI BibTeX RDF
12	Jason Cong, Yean-Yow Hwang	Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.	FPGA	1997	DBLP DOI BibTeX RDF
12	Roger F. Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring	FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again).	FCCM	1997	DBLP DOI BibTeX RDF
12	Kuo-Rueih Ricky Pan, Massoud Pedram	FPGA synthesis for minimum area, delay and power.	ED&TC	1996	DBLP DOI BibTeX RDF
12	Christoph Scholl 0001, Paul Molitor	Communication based FPGA synthesis for multi-output Boolean functions.	ASP-DAC	1995	DBLP DOI BibTeX RDF
12	Ted Stanion, Carl Sechen	A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis.	DAC	1995	DBLP DOI BibTeX RDF
12	Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram	FPGA Synthesis Using Function Decomposition.	ICCD	1994	DBLP DOI BibTeX RDF
12	Ricardo P. Jacobi, Anne-Marie Trullemans	A new logic minimization method for multiplexor-based FPGA synthesis.	EURO-DAC	1993	DBLP DOI BibTeX RDF
12	Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula	BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis.	DAC	1993	DBLP DOI BibTeX RDF
11	Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer	Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi	A High Performance Parallel FIR Filters Generation Tool.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
11	Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton	Topologically constrained logic synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
8	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
8	Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga	Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Tirath Ramdas, Gregory K. Egan, David Abramson 0001, Kim K. Baldridge	Run-time thread sorting to expose data-level parallelism.	ASAP	2008	DBLP DOI BibTeX RDF
8	Sin Man Cheang, Kin-Hong Lee, Kwong-Sak Leung	Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
8	Wei Li 0131, Zibin Dai, Tao Chen 0047, Tao Meng, Xuan S. Yang	Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit.	APPT	2007	DBLP DOI BibTeX RDF
8	Marcelo Schiavon Porto, Luciano Volcan Agostini, Leandro Rosa, Altamiro Amadeu Susin, Sergio Bampi	High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications.	PSIVT	2007	DBLP DOI BibTeX RDF	Motion estimation, hardware architecture, FPGA design
8	Mark G. Arnold	A RISC Processor with Redundant LNS Instructions.	DSD	2006	DBLP DOI BibTeX RDF
8	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
8	Raymond R. Hoare, Zhu Ding, Alex K. Jones	Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches.	SC	2006	DBLP DOI BibTeX RDF
8	Uwe Meyer-Bäse, Jiajia Chen 0002, Chip-Hong Chang, Andrew G. Dempster	A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli	An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms.	FPL	2002	DBLP DOI BibTeX RDF
8	Jim Armstrong, Amy Bell, Gail Gray	An Intra-Disciplinary Capstone Project in Digital Filter Design.	MSE	2001	DBLP DOI BibTeX RDF
8	Jason Cong, Kenneth Yan	Synthesis for FPGAs with embedded memory blocks.	FPGA	2000	DBLP DOI BibTeX RDF