Search results for "Fan-in"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Valeriu Beiu, Sorin Draghici, Hanna E. Makaruk	On limited fan-in optimal neural networks.	SBRN	1997	DBLP DOI BibTeX RDF	fan-in values, chip size, Shannon decomposition, VLSI, Boolean functions, feedforward neural networks, neural chips, threshold circuits
96	Liming Cai, Jianer Chen, Johan Håstad	Circuit Bottom Fan-in and Computational Power.	CCC	1997	DBLP DOI BibTeX RDF	computational complexity, lower bound, circuit complexity, alternating Turing machine
86	Ramachandran Vaidyanathan, Sudharani Nadella	Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms.	IPPS	1996	DBLP DOI BibTeX RDF	Multiple bus networks, Fan-in algorithms, Fault-tolerance, Parallel processing, Interconnection networks
78	Jon Alfredsson, Snorre Aunet, Bengt Oelmann	Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure.	VLSI Design	2007	DBLP DOI BibTeX RDF
74	Dana Angluin, James Aspnes, Jiang Chen, Yinghua Wu	Learning a circuit by injecting values.	STOC	2006	DBLP DOI BibTeX RDF	learning, circuit, gene regulatory network
74	Jon Ahn, Kyungtae Lee	A Computational Method for the Performance Modeling and Design of a Ducted Fan System.	AsiaSim	2004	DBLP DOI BibTeX RDF
58	Marius Marin, Arie van Deursen, Leon Moonen	Identifying Crosscutting Concerns Using Fan-In Analysis.	ACM Trans. Softw. Eng. Methodol.	2007	DBLP DOI BibTeX RDF	fan-in metric, reverse engineering, Aspect-oriented programming, crosscutting concerns
55	Sorin Cotofana, Stamatis Vassiliadis	delta-Bit serial binary addition with linear threshold networks.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
50	Arkadev Chattopadhyay	Discrepancy and the Power of Bottom Fan-in in Depth-three Circuits.	FOCS	2007	DBLP DOI BibTeX RDF
50	Y. Tsiatouhas, Angela Arapoyanni	High fan-in differential current mirror logic.	ISCAS	2006	DBLP DOI BibTeX RDF
50	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi	A high speed and leakage-tolerant domino logic for high fan-in gates.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high speed, noise immunity, deep submicron, fan-in, domino
49	Arshad Ali, Ramachandran Vaidyanathan	Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple Bus Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	ASCEND/DESCEND algorithms, FAN-IN algorithms, multiple bus networks, synchronous parallelism, scheduling, parallel algorithms
41	Jinhui Chen, Lawrence T. Clark, Yu Cao	Robust Design of High Fan-In/Out Subthreshold Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
41	Dinesh Somasekhar, Kaushik Roy 0001	LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
40	Hua Xiang 0001, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho	Logical and physical restructuring of fan-in trees.	ISPD	2010	DBLP DOI BibTeX RDF	symmetric-function fan-in tree, restructure, commutative
40	Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi	Noise-tolerant high fan-in dynamic CMOS circuit design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits
37	Peter Høyer, Robert Spalek	Quantum Circuits with Unbounded Fan-out.	STACS	2003	DBLP DOI BibTeX RDF
37	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
37	Thomas Nowotny, Ramón Huerta, Henry D. I. Abarbanel, Mikhail I. Rabinovich	Self-organization in the olfactory system: one shot odor recognition in insects.	Biol. Cybern.	2005	DBLP DOI BibTeX RDF	Synaptic convergence, Information coding, Pattern recognition, Olfaction, Fan-out, Fan-in
37	Clark F. Olson	Connectionist networks for feature indexing and object recognition.	CVPR	1996	DBLP DOI BibTeX RDF	feature indexing, feature extraction, object recognition, object recognition, image features, feedforward neural nets, geometric hashing, fan-out, fan-in, connectionist networks
36	Zhide Zeng, Jihua Chen, Pengxia Liu	A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Parallel Test Generation, Fault Parallelism, Fault Partitioning, Output Fan-in Cones, Input Fan-out Cones, Speed-up Ratio
36	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
32	Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen	Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
32	Marius Marin, Arie van Deursen, Leon Moonen	Identifying Aspects Using Fan-In Analysis.	WCRE	2004	DBLP DOI BibTeX RDF
32	Nader H. Bshouty, Thomas R. Hancock, Lisa Hellerstein	Learning Boolean Read-Once Formulas with Arbitrary Symmetric and Constant Fan-in Gates.	COLT	1992	DBLP DOI BibTeX RDF
31	György Turán, Farrokh Vatan	On the Computation of Boolean Functions by Analog Circuits of Bounded Fan-in (Extended Abstract)	FOCS	1994	DBLP DOI BibTeX RDF	explicit nonlinear lower bounds, computation of Boolean functions, bounded fan-in, real-valued functions, sign-representation, n-variable function, piecewise linear circuits, complexity, upper bounds, nondeterminism, analog circuits
31	Matthias Krause 0001, Stephan Waack	Variation Ranks of Communication Matrices and Lower Bounds for Depth Two Circuits Having Symmetric Gates with Unbounded Fan-In	FOCS	1991	DBLP DOI BibTeX RDF	MOD m gate, communication matrices, depth two circuits, symmetric gates, unbounded fan-in, exponential lower bound, variation rank, threshold gate
31	Douglas B. West, Prithviraj Banerjee	On the Construction of Communication Networks Satisfying Bounded Fan-In of Service Ports.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	bounded fan-in, service ports, graph-theoretic problem, graph theory, linear programming, linear programming, computer networks, communication networks, users, bipartite graph
28	Qi Zhao 0006, Jun (Jim) Xu, Abhishek Kumar 0003	Detection of Super Sources and Destinations in High-Speed Networks: Algorithms, Analysis and Evaluation.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
28		HiFi: Network-centric query processing in the physical world.	ICDE Workshops	2005	DBLP DOI BibTeX RDF
28	Zeev Dvir, Amir Shpilka	Locally decodable codes with 2 queries and polynomial identity testing for depth 3 circuits.	STOC	2005	DBLP DOI BibTeX RDF	depth 3 circuits, locally decodable codes, polynomial identity testing
28	Sorin Cotofana, Stamatis Vassiliadis	Periodic symmetric functions, serial addition, and multiplication with neural networks.	IEEE Trans. Neural Networks	1998	DBLP DOI BibTeX RDF
28	Dima Grigoriev, Marek Karpinski	A Zero-Test and an Interpolation Algorithm for the Shifted Sparse Polynominals.	AAECC	1993	DBLP DOI BibTeX RDF
28	Thomas K. Callaway, Earl E. Swartzlander Jr.	Estimating the power consumption of CMOS adders.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
28	Zhi-Li Zhang, David A. Mix Barrington, Jun Tarui	Computing Symmetric Functions with AND/OR Circuits and a Single MAJORITY Gate.	STACS	1993	DBLP DOI BibTeX RDF
27	Keshuo Sun, Haiying Gao	Adaptively secure CP-ABE for circuits with fan-in n and fan-out 1.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
27	Keshuo Sun, Haiying Gao	Adaptively Secure KP-ABE For Circuits With Fan-In n And Fan-Out 1.	Comput. J.	2023	DBLP DOI BibTeX RDF
27	Min Yang, Chengkun Cai, Yize Liang, Lei Shen, Yanjun Zhu, Hua Zhang, Chaonan Yao, Yuchen Shao, Lei Zhang, Changkun Yan, Liubo Yang, Ruichun Wang, Jun Chu, Jian Wang 0060	19-Core SDM Self-Homodyne Coherent Transmission using Fan-In/Fan-Out Photonic Lantern.	OFC	2023	DBLP DOI BibTeX RDF
27	Kohei Ozaki, Yoshifumi Koike, Akito Nishimura	Bundle-type fan-in/fan-out device for 4-core multi-core fiber with high return loss.	OFC	2023	DBLP DOI BibTeX RDF
27	Yang Wang, Xutao Wang, Zhiqun Yang, Yaping Liu, Zhanhua Huang, Lin Zhang	Fan-in/Fan-out for Heterogeneous 19-core Fibers Based on Metasurfaces with Nonuniform Phase Plates.	OFC	2023	DBLP DOI BibTeX RDF
27	Shadi Omranpour, Seyed Amir Hashemi	Increasing fan-in and fan-out of the quantum phase slip junction-based logic gates.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
27	Junjie Xiong, Lin Ma 0008, Zuyuan He	Low Loss All-Fiber Fan-in/Fan-out Device for Coupled-Core Four-Core Fibers.	OECC/PSC	2022	DBLP DOI BibTeX RDF
27	Takahiro Kikuchi, Osamu Shimakawa, Hidehisa Tazawa	Low insertion loss and high return loss fiber bundle fan-in/fan-out for four-core multi-core fiber.	OECC/PSC	2022	DBLP DOI BibTeX RDF
27	Masanori Takahashi, Kohei Kawasaki, Ryuichi Sugizaki, Yoshihiro Arashitani	Fan-in/Fan-out for multicore fibers.	OECC/PSC	2022	DBLP DOI BibTeX RDF
27	Tomoaki Kiriyama, Katsuhiro Iwasaki, Katsuya Kito, Takashi Kato	Free-Space Coupling Type Fan-in/Fan-out Device for 4-Core Fiber with Low Insertion Loss.	OFC	2022	DBLP BibTeX RDF
27	Zhijie Yang, Lei Wang, Yao Wang, LingHui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, Weixia Xu	Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons.	DAC	2022	DBLP DOI BibTeX RDF
27	Haisong Jiang, Yasuhiro Hinokuma, Sampad Ghosh, Ryota Kuwahata, Kiichi Hamamoto	Concept Demonstration of 3D Waveguides Shuffle Converter for Multi-Core Fiber/Single-Mode Fiber Fan-in Fan-out Configuration Toward Over 1, 000 Port Count.	IEICE Trans. Electron.	2021	DBLP DOI BibTeX RDF
27	Yi-Chun Ling, Shuyun Yuan, S. J. Ben Yoo	Low-Loss Three-Dimensional Fan-in/Fan-out Devices for Multi-Core Fiber Integration.	OFC	2021	DBLP BibTeX RDF
27	Taketoshi Takahata, Asumi Kaya, Yuta Ozawa, Yousuke Minagawa, Tetsuya Kobayashi	High Reliability Fan-in / Fan-out Device with Isolator for Multi-core fibre Based on Free Space Optics.	ECOC	2021	DBLP DOI BibTeX RDF
27	Michael L. Schneider, K. Segall	Fan-out and Fan-in properties of superconducting neuromorphic circuits.	CoRR	2020	DBLP BibTeX RDF
27	Lin Gan, Jiajun Zhou, Li Shen, Xiancong Guo, Yanlin Wang, Chen Yang, Weijun Tong, Li Xia, Songnian Fu, Ming Tang 0005, Deming Liu	Ultra-Low Crosstalk Fused Taper Type Fan-In/Fan-Out Devices for Multicore Fibers.	OFC	2019	DBLP BibTeX RDF
27	Juan Carlos Alvarado-Zacarias, Jose Enrique Antonio-Lopez, Md. Selim Habib, Stefan Gausmann, Ning Wang, Daniel Cruz-Delgado, Axel Schülzgen, Adrian Amezcua Correa, Louis-Anne de Montmorillon, Pierre Sillard, Rodrigo Amezcua Correa	Low-Loss 19 Core Fan-in/Fan-out Device using Reduced-Cladding Graded Index Fibers.	OFC	2019	DBLP BibTeX RDF
27	Kota Shikama, Yoshiteru Abe, Toshiki Kishi, Koji Takeda, Takuro Fujii, Hidetaka Nishi, Takashi Matsui, Atsushi Aratake, Kazuhide Nakajima, Shinji Matsuo	Multicore-Fiber LC Receptacle with Compact Fan-in/Fan-out for Short-Reach Transceivers.	OFC	2018	DBLP BibTeX RDF
27	Kota Shikama, Yoshiteru Abe, Hirotaka Ono 0002, Atsushi Aratake	Low-loss fiber-bundle-type fan-in/fan-out device for 6-mode 19-core fiber.	OFC	2017	DBLP BibTeX RDF
27	Yongmin Jung, John R. Hayes, Shaif-Ul Alam, David J. Richardson	Multicore Fibre Fan-In/Fan-Out Device using Fibre Optic Collimators.	ECOC	2017	DBLP DOI BibTeX RDF
27	Yusaku Tottori, Hiroshi Tsuboya, Tetsuya Kobayashi	Multi functionality demonstration for multi core fiber fan-in/fan-out devices using free space optics.	OFC	2014	DBLP DOI BibTeX RDF
27	Yunhong Ding, Feihong Ye, Christophe Peucheret, Haiyan Ou, Yutaka Miyamoto, Toshio Morioka	On-chip grating coupler array on the SOI platform for fan-in/fan-out of multi-core fibers with low insertion loss and crosstalk.	ECOC	2014	DBLP DOI BibTeX RDF
27	Alessandro Murgia, Roberto Tonelli, Giulio Concas, Michele Marchesi, Steve Counsell	Parameter-based refactoring and the relationship with fan-in/fan-out coupling.	J. Object Technol.	2012	DBLP DOI BibTeX RDF
27	Alessandro Murgia, Roberto Tonelli, Michele Marchesi, Giulio Concas, Steve Counsell, Janet McFall, Stephen Swift	Refactoring and its Relationship with Fan-in and Fan-out: An Empirical Study.	CSMR	2012	DBLP DOI BibTeX RDF
27	Asma Mubarak, Steve Counsell, Robert M. Hierons	A Longitudinal Study of Fan-In and Fan-Out Coupling in Open-Source Systems.	Int. J. Inf. Syst. Model. Des.	2011	DBLP DOI BibTeX RDF
27	Alessandro Murgia, Michele Marchesi, Giulio Concas, Roberto Tonelli, Steve Counsell	Parameter-Based Refactoring and the Relationship with Fan-in/Fan-out Coupling.	ICST Workshops	2011	DBLP DOI BibTeX RDF
27	Emal Nasseri, Steve Counsell, Ewan D. Tempero	An Empirical Study of Fan-In and Fan-Out in Java OSS.	SERA	2010	DBLP DOI BibTeX RDF	Coupling, cohesion, empirical
27	Asma Mubarak, Steve Counsell, Robert M. Hierons	An Evolutionary Study of Fan-in and Fan-out Metrics in OSS.	RCIS	2010	DBLP DOI BibTeX RDF
27	Yacoub M. El-Ziq	Logic design automation of MOS combinational networks with fan-in, fan-out constraints.	DAC	1978	DBLP BibTeX RDF
27	Stephen Y. H. Su, Chong-Woo Nam	Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
27	Gerhard L. Hollander	Effect of Fan-In and Fan-Out Limitations on the Value of Computer Circuits.	IEEE Trans. Electron. Comput.	1963	DBLP DOI BibTeX RDF
26	Mariano Ceccato, Marius Marin, Kim Mens, Leon Moonen, Paolo Tonella, Tom Tourwé	A Qualitative Comparison of Three Aspect Mining Techniques.	IWPC	2005	DBLP DOI BibTeX RDF	fan-in analysis, aspect-oriented programming, crosscutting concerns, concept analysis, aspect mining
26	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits
23	Zohar Shay Karnin, Amir Shpilka	Black Box Polynomial Identity Testing of Generalized Depth-3 Arithmetic Circuits with Bounded Top Fan-In.	CCC	2008	DBLP DOI BibTeX RDF	PIT, depth-3, arithmetic circuit, deterministic, polynomial identity testing
23	Massimo Alioto, Gaetano Palumbo	Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee	A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates.	DAC	2006	DBLP DOI BibTeX RDF	dynamic gates, keeper design, reliability, VLSI, robustness, low-power design, process variation
23	Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications .	ISVLSI	2004	DBLP DOI BibTeX RDF
23	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates.	ISQED	2004	DBLP DOI BibTeX RDF
23	Ming-Bo Lin	On the design of fast large fan-in CMOS multiplexers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
23	Pascal Hénon, Pierre Ramet, Jean Roman	A Mapping and Scheduling Algorithm for Parallel Sparse Fan-In Numerical Factorization.	Euro-Par	1999	DBLP DOI BibTeX RDF
23	Shaoyi Wang	Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
18	Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni	A Current Mode, Parallel, Two-Rail Code Checker.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
18	Marc García-Arnau, David Pérez, Alfonso Rodríguez-Patón, Petr Sosík	On the power of elementary features in spiking neural P systems.	Nat. Comput.	2008	DBLP DOI BibTeX RDF	Normal form, Membrane computing, P system, Spiking neuron
18	Richard L. Graham, Galen M. Shipman	MPI Support for Multi-core Architectures: Optimized Shared Memory Collectives.	PVM/MPI	2008	DBLP DOI BibTeX RDF	MPI_Bcast, MPI_Reduce, MPI_Allreduce, Shared-Memory, Collectives
18	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
18	Lucas Layman, Gunnar Kudrjavets, Nachiappan Nagappan	Iterative identification of fault-prone binaries using in-process metrics.	ESEM	2008	DBLP DOI BibTeX RDF	code churn, regression, statistical models, fault prediction
18	Adam Barker, Jon B. Weissman, Jano I. van Hemert	Eliminating the middleman: peer-to-peer dataflow.	HPDC	2008	DBLP DOI BibTeX RDF	decentralised orchestration, workflow optimisation
18	Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals	A High-Speed Optical Multi-Drop Bus for Computer Interconnections.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
18	Hui Wei	A hierarchical model for structure learning based on the physiological characteristics of neurons.	Frontiers Comput. Sci. China	2007	DBLP DOI BibTeX RDF	representation, associative memory, structure learning, computational neuroscience
18	Nitish D. Patel, Sing Kiong Nguang, George G. Coghill	Neural Network Implementation Using Bit Streams.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
18	John H. Reppy, Yingqi Xiao	Specialization of CML message-passing primitives.	POPL	2007	DBLP DOI BibTeX RDF	static analysis, message passing, ML, concurrent languages
18	Yuval Ishai, Eyal Kushilevitz, Rafail Ostrovsky, Amit Sahai	Zero-knowledge from secure multiparty computation.	STOC	2007	DBLP DOI BibTeX RDF	cryptography, zero-knowledge, secure computation, black-box reductions
18	Young Lee, Jeong Yang, Kai H. Chang	Metrics and Evolution in Open Source Software.	QSIC	2007	DBLP DOI BibTeX RDF
18	Benny Applebaum, Yuval Ishai, Eyal Kushilevitz	Cryptography with Constant Input Locality.	CRYPTO	2007	DBLP DOI BibTeX RDF
18	R. Ian Bull, Margaret-Anne D. Storey, Jean-Marie Favre, Marin Litoiu	An Architecture to Support Model Driven Software Visualization.	ICPC	2006	DBLP DOI BibTeX RDF
18	Abdelwahab Hamou-Lhadj, Timothy Lethbridge	Summarizing the Content of Large Traces to Facilitate the Understanding of the Behaviour of a Software System.	ICPC	2006	DBLP DOI BibTeX RDF	Reverse engineering, Program comprehension, Dynamic analysis, Design recovery
18	Krzysztof Juszczyszyn, Grzegorz Kolaczek	Assessing the Uncertainty of Communication Patterns in Distributed Intrusion Detection System.	KES (2)	2006	DBLP DOI BibTeX RDF
18	Michael K. Cheng, Bruce E. Moision, Jon Hamkins, Michael A. Nakashima	An interleaver implementation for the serially concatenated pulse-position modulation decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Srivastav Sethupathy, Nohpill Park, Marcin Paprzycki	Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach.	SYNASC	2005	DBLP DOI BibTeX RDF
18	Ryan Williams 0001	Parallelizing time with polynomial circuits.	SPAA	2005	DBLP DOI BibTeX RDF	parallel speedup, circuit complexity, alternation
18	Hosam M. Mahmoud, Tatsuie Tsukiji	Limit laws for terminal nodes in random circuits with restricted fan-out: a family of graphs generalizing binary search trees.	Acta Informatica	2004	DBLP DOI BibTeX RDF
18	Yuanyuan Yang 0001, Jianchao Wang	A Class of Multistage Conference Switching Networks for Group Communication.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	conference networks, many-to-many connections, group communication, multistage interconnection networks, switching, self-routing, Conferencing
18	Robert Ball, Glenn A. Fink, Chris North 0001	Home-centric visualization of network traffic for security administration.	VizSEC	2004	DBLP DOI BibTeX RDF	security, information visualization, networks
18	Kazushige Terui	Proof Nets and Boolean Circuits.	LICS	2004	DBLP DOI BibTeX RDF
18	Kwang-Il Oh, Lee-Sup Kim	A clock delayed sleep mode domino logic for wide dynamic OR gate.	ISLPED	2003	DBLP DOI BibTeX RDF	clock delay, low power, leakage, sleep mode, dynamic circuits