Search results for "Fan-out"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Dan R. Olsen, Stephen Bart Wood	Fan-out: measuring human control of multiple robots.	CHI	2004	DBLP DOI BibTeX RDF	human-robot interaction, fan-out, multiple robots
108	Kolar L. Kodandapani, Sharad C. Seth	On Combinational Networks with Restricted Fan-Out.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	single fault location, Characterization of fan-out-free networks, counting of fan-out-free, fan-out-free networks, localized fan outs, functional decomposition, combinational networks, multiple fault detection
94	Yen-Chun Lin, Li-Ling Hung	Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Depth-size optimal, parallel prefix circuits, fan-out
84	Yen-Chun Lin, Yao-Hsien Hsu, Chun-Keng Liu	Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	depth-size optimal, prefix circuits, size optimal, parallel algorithms, depth, fan-out
73	Yen-Chun Lin, Jun-Wei Hsiao	A New Approach to Constructing Optimal Prefix Circuits with Small Depth.	ISPAN	2002	DBLP DOI BibTeX RDF	depth-size optimal, prefix circuits, parallel algorithms, fan-out
72	Yen-Chun Lin, Chao-Cheng Shih	A New Class of Depth-Size Optimal Parallel Prefix Circuits.	J. Supercomput.	1999	DBLP DOI BibTeX RDF	depth-size optimal, unbounded fan-out, VLSI, Combinational circuits, parallel prefix
61	Peter Høyer, Robert Spalek	Quantum Circuits with Unbounded Fan-out.	STACS	2003	DBLP DOI BibTeX RDF
59	Thomas H. Spencer, Jacob Savir	Layout Influences Testability.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	reconvergent fan-out, Boolean difference, layout, masking, fan-out
57	Ramachandran Vaidyanathan, Sudharani Nadella	Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms.	IPPS	1996	DBLP DOI BibTeX RDF	Multiple bus networks, Fan-in algorithms, Fault-tolerance, Parallel processing, Interconnection networks
54	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
54	Xiaohong Jiang 0001, Achille Pattavina, Susumu Horiguchi	Rearrangeable f-cast multi-log2 N networks.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
54	Pratul Dublish, Joachim Biskup, Yehoshua Sagiv	Optimizatioin of a Subclass of Conjunctive Queries.	ICDT	1990	DBLP DOI BibTeX RDF
50	Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl	Prediction of interconnect fan-out distribution using Rent's rule.	SLIP	2000	DBLP DOI BibTeX RDF	fan-out distribution, interconnect network prediction, Rent's rule
50	K. Lai, Parag K. Lala	Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	fan-out-free circuit, output count, test generation, Multiple faults
50	Thomas Nowotny, Ramón Huerta, Henry D. I. Abarbanel, Mikhail I. Rabinovich	Self-organization in the olfactory system: one shot odor recognition in insects.	Biol. Cybern.	2005	DBLP DOI BibTeX RDF	Synaptic convergence, Information coding, Pattern recognition, Olfaction, Fan-out, Fan-in
50	Clark F. Olson	Connectionist networks for feature indexing and object recognition.	CVPR	1996	DBLP DOI BibTeX RDF	feature indexing, feature extraction, object recognition, object recognition, image features, feedforward neural nets, geometric hashing, fan-out, fan-in, connectionist networks
49	Zhide Zeng, Jihua Chen, Pengxia Liu	A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Parallel Test Generation, Fault Parallelism, Fault Partitioning, Output Fan-in Cones, Input Fan-out Cones, Speed-up Ratio
49	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
45	Sandra Mau, John M. Dolan	Scheduling for humans in multirobot supervisory control.	IROS	2007	DBLP DOI BibTeX RDF
44	Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch	Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.	DATE	2003	DBLP DOI BibTeX RDF
43	Pratul Dublish, S. N. Maheshwari	On O(N²) Equivalence Algorithm for Fan-Out Free Queries.	ICDT	1988	DBLP DOI BibTeX RDF
43	Pratul Dublish, S. N. Maheshwari	An O(n²) Algorithm for Fan-Out Free Query Optimization.	FSTTCS	1987	DBLP DOI BibTeX RDF
43	Tanja Braun, K.-F. Becker, S. Raatz, V. Bader, Jörg Bauer 0002, Rolf Aschenbrenner, S. Voges, Tina Thomas, R. Kahle, Klaus-Dieter Lang	From fan-out wafer to fan-out panel level packaging.	ECCTD	2015	DBLP DOI BibTeX RDF
41	Hosam M. Mahmoud, Tatsuie Tsukiji	Limit laws for terminal nodes in random circuits with restricted fan-out: a family of graphs generalizing binary search trees.	Acta Informatica	2004	DBLP DOI BibTeX RDF
41	Jacob W. Crandall, Mary L. Cummings	Developing performance metrics for the supervisory control of multiple robots.	HRI	2007	DBLP DOI BibTeX RDF	multi-robot teams, supervisory control, fan-out
40	Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara	Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	11 fan-out of four, 11FO4, Synergistic Processor Element, private memory, streaming processing, Cell processor, multimedia processing, scratch pad memory
40	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
35	Keshuo Sun, Haiying Gao	Adaptively secure CP-ABE for circuits with fan-in n and fan-out 1.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
35	Keshuo Sun, Haiying Gao	Adaptively Secure KP-ABE For Circuits With Fan-In n And Fan-Out 1.	Comput. J.	2023	DBLP DOI BibTeX RDF
35	Min Yang, Chengkun Cai, Yize Liang, Lei Shen, Yanjun Zhu, Hua Zhang, Chaonan Yao, Yuchen Shao, Lei Zhang, Changkun Yan, Liubo Yang, Ruichun Wang, Jun Chu, Jian Wang 0060	19-Core SDM Self-Homodyne Coherent Transmission using Fan-In/Fan-Out Photonic Lantern.	OFC	2023	DBLP DOI BibTeX RDF
35	Kohei Ozaki, Yoshifumi Koike, Akito Nishimura	Bundle-type fan-in/fan-out device for 4-core multi-core fiber with high return loss.	OFC	2023	DBLP DOI BibTeX RDF
35	Yang Wang, Xutao Wang, Zhiqun Yang, Yaping Liu, Zhanhua Huang, Lin Zhang	Fan-in/Fan-out for Heterogeneous 19-core Fibers Based on Metasurfaces with Nonuniform Phase Plates.	OFC	2023	DBLP DOI BibTeX RDF
35	Shadi Omranpour, Seyed Amir Hashemi	Increasing fan-in and fan-out of the quantum phase slip junction-based logic gates.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
35	Junjie Xiong, Lin Ma 0008, Zuyuan He	Low Loss All-Fiber Fan-in/Fan-out Device for Coupled-Core Four-Core Fibers.	OECC/PSC	2022	DBLP DOI BibTeX RDF
35	Takahiro Kikuchi, Osamu Shimakawa, Hidehisa Tazawa	Low insertion loss and high return loss fiber bundle fan-in/fan-out for four-core multi-core fiber.	OECC/PSC	2022	DBLP DOI BibTeX RDF
35	Masanori Takahashi, Kohei Kawasaki, Ryuichi Sugizaki, Yoshihiro Arashitani	Fan-in/Fan-out for multicore fibers.	OECC/PSC	2022	DBLP DOI BibTeX RDF
35	Tomoaki Kiriyama, Katsuhiro Iwasaki, Katsuya Kito, Takashi Kato	Free-Space Coupling Type Fan-in/Fan-out Device for 4-Core Fiber with Low Insertion Loss.	OFC	2022	DBLP BibTeX RDF
35	Zhijie Yang, Lei Wang, Yao Wang, LingHui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, Weixia Xu	Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons.	DAC	2022	DBLP DOI BibTeX RDF
35	Haisong Jiang, Yasuhiro Hinokuma, Sampad Ghosh, Ryota Kuwahata, Kiichi Hamamoto	Concept Demonstration of 3D Waveguides Shuffle Converter for Multi-Core Fiber/Single-Mode Fiber Fan-in Fan-out Configuration Toward Over 1, 000 Port Count.	IEICE Trans. Electron.	2021	DBLP DOI BibTeX RDF
35	Yi-Chun Ling, Shuyun Yuan, S. J. Ben Yoo	Low-Loss Three-Dimensional Fan-in/Fan-out Devices for Multi-Core Fiber Integration.	OFC	2021	DBLP BibTeX RDF
35	Taketoshi Takahata, Asumi Kaya, Yuta Ozawa, Yousuke Minagawa, Tetsuya Kobayashi	High Reliability Fan-in / Fan-out Device with Isolator for Multi-core fibre Based on Free Space Optics.	ECOC	2021	DBLP DOI BibTeX RDF
35	Michael L. Schneider, K. Segall	Fan-out and Fan-in properties of superconducting neuromorphic circuits.	CoRR	2020	DBLP BibTeX RDF
35	Lin Gan, Jiajun Zhou, Li Shen, Xiancong Guo, Yanlin Wang, Chen Yang, Weijun Tong, Li Xia, Songnian Fu, Ming Tang 0005, Deming Liu	Ultra-Low Crosstalk Fused Taper Type Fan-In/Fan-Out Devices for Multicore Fibers.	OFC	2019	DBLP BibTeX RDF
35	Juan Carlos Alvarado-Zacarias, Jose Enrique Antonio-Lopez, Md. Selim Habib, Stefan Gausmann, Ning Wang, Daniel Cruz-Delgado, Axel Schülzgen, Adrian Amezcua Correa, Louis-Anne de Montmorillon, Pierre Sillard, Rodrigo Amezcua Correa	Low-Loss 19 Core Fan-in/Fan-out Device using Reduced-Cladding Graded Index Fibers.	OFC	2019	DBLP BibTeX RDF
35	Kota Shikama, Yoshiteru Abe, Toshiki Kishi, Koji Takeda, Takuro Fujii, Hidetaka Nishi, Takashi Matsui, Atsushi Aratake, Kazuhide Nakajima, Shinji Matsuo	Multicore-Fiber LC Receptacle with Compact Fan-in/Fan-out for Short-Reach Transceivers.	OFC	2018	DBLP BibTeX RDF
35	Kota Shikama, Yoshiteru Abe, Hirotaka Ono 0002, Atsushi Aratake	Low-loss fiber-bundle-type fan-in/fan-out device for 6-mode 19-core fiber.	OFC	2017	DBLP BibTeX RDF
35	Yongmin Jung, John R. Hayes, Shaif-Ul Alam, David J. Richardson	Multicore Fibre Fan-In/Fan-Out Device using Fibre Optic Collimators.	ECOC	2017	DBLP DOI BibTeX RDF
35	Yusaku Tottori, Hiroshi Tsuboya, Tetsuya Kobayashi	Multi functionality demonstration for multi core fiber fan-in/fan-out devices using free space optics.	OFC	2014	DBLP DOI BibTeX RDF
35	Yunhong Ding, Feihong Ye, Christophe Peucheret, Haiyan Ou, Yutaka Miyamoto, Toshio Morioka	On-chip grating coupler array on the SOI platform for fan-in/fan-out of multi-core fibers with low insertion loss and crosstalk.	ECOC	2014	DBLP DOI BibTeX RDF
35	Alessandro Murgia, Roberto Tonelli, Giulio Concas, Michele Marchesi, Steve Counsell	Parameter-based refactoring and the relationship with fan-in/fan-out coupling.	J. Object Technol.	2012	DBLP DOI BibTeX RDF
35	Alessandro Murgia, Roberto Tonelli, Michele Marchesi, Giulio Concas, Steve Counsell, Janet McFall, Stephen Swift	Refactoring and its Relationship with Fan-in and Fan-out: An Empirical Study.	CSMR	2012	DBLP DOI BibTeX RDF
35	Asma Mubarak, Steve Counsell, Robert M. Hierons	A Longitudinal Study of Fan-In and Fan-Out Coupling in Open-Source Systems.	Int. J. Inf. Syst. Model. Des.	2011	DBLP DOI BibTeX RDF
35	Alessandro Murgia, Michele Marchesi, Giulio Concas, Roberto Tonelli, Steve Counsell	Parameter-Based Refactoring and the Relationship with Fan-in/Fan-out Coupling.	ICST Workshops	2011	DBLP DOI BibTeX RDF
35	Emal Nasseri, Steve Counsell, Ewan D. Tempero	An Empirical Study of Fan-In and Fan-Out in Java OSS.	SERA	2010	DBLP DOI BibTeX RDF	Coupling, cohesion, empirical
35	Asma Mubarak, Steve Counsell, Robert M. Hierons	An Evolutionary Study of Fan-in and Fan-out Metrics in OSS.	RCIS	2010	DBLP DOI BibTeX RDF
35	Yacoub M. El-Ziq	Logic design automation of MOS combinational networks with fan-in, fan-out constraints.	DAC	1978	DBLP BibTeX RDF
35	Stephen Y. H. Su, Chong-Woo Nam	Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
35	Gerhard L. Hollander	Effect of Fan-In and Fan-Out Limitations on the Value of Computer Circuits.	IEEE Trans. Electron. Comput.	1963	DBLP DOI BibTeX RDF
32	Shin-ichiro Tago, Shuichi Ueno	Optimal Realization of Hypercubes by Three-Dimensional Space-Invariant Optical Interconnections.	ISPAN	1997	DBLP DOI BibTeX RDF
32	Michele Favalli, Piero Olivo, Bruno Riccò	A novel critical path heuristic for fast fault grading.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
32	Fadi Maamari, Janusz Rajski	A method of fault simulation based on stem regions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
32	Jonathan M. Whetten, Michael A. Goodrich	Specialization, fan-out, and multi-human/multi-robot supervisory control.	HRI	2010	DBLP DOI BibTeX RDF	human-robot interaction, multi-user interface
31	Qi Zhao 0006, Jun (Jim) Xu, Abhishek Kumar 0003	Detection of Super Sources and Destinations in High-Speed Networks: Algorithms, Analysis and Evaluation.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
31	Jinhui Chen, Lawrence T. Clark, Yu Cao	Robust Design of High Fan-In/Out Subthreshold Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
30	A. Yavuz Oruç, Ajai Thirumalai	A Systematic Design of Cellular Permutation Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cellular permutation arrays, coset decompositions, permutation cell, coset generator, target network, multiprocessor interconnection networks, network topology, cellular arrays, cost function, propagation delay, fan-out, fan-in
29	Thomas K. Callaway, Earl E. Swartzlander Jr.	Estimating the power consumption of CMOS adders.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
29	Binay Sugla, David A. Carlson	Extreme Area-Time Tradeoffs in VLSI.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder
29	Bhargab B. Bhattacharya, Bidyut Gupta	On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	fan-out-free functions, N-equivalence classes, P-equivalence classes, short circuit faults, fault detection, stuck-at faults, Bridging faults, combinational logic, unate functions
29	Fred U. Rosenberger, Donald F. Wann	A Computer Aided Procedure for Performing Static Loading Validation of Digital Logic Systems.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	static loading validation, digital design aids, fan-out computations, logic design aids, Computer aided design, loading
29	Jacob Savir	Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Inversion parity, reconvergent fan-out, unate function
29	John C. Sutton, Jon G. Bredeson	Minimal Redundant Logic for High Reliability and Irredundant Testability.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Completely testable for single and multiple faults, control inputs and outputs, multilevel fan out free circuits, redundant connections, static logic hazard, triple modular redundancy
29	Vinod K. Agarwal, Gerald M. Masson	Generic Fault Characterizations for Table Look-Up Coverage Bounding.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	single and multiple fault detection, Coverage bounds, coverage table, fault vectors, generic representations, L-expressions, internal fan-out-free networks
23	Kazuo Iwama	Classic and Quantum Network Coding.	ISPAN	2005	DBLP DOI BibTeX RDF
21	Mihir R. Choudhury, Kartik Mohanram	Reliability Analysis of Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Xiaoyu Wang, Hongyan Liu, Daoxin Er	HIDS: a multifunctional generator of hierarchical data streams.	Data Base	2009	DBLP DOI BibTeX RDF	data mining, data stream, data generator, computing technique
21	Qinghua Liu, Malgorzata Marek-Sadowska	Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Bo-Hyun Wang, Byung-Wook Lee	An Efficient Search Algorithm for High-Dimensional Indexing Using Cell Based MBR.	ICCSA (1)	2006	DBLP DOI BibTeX RDF
21	Francisco-Javier Veredas, Jordi Carrabina	Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.	PATMOS	2005	DBLP DOI BibTeX RDF
21	Jeffrey V. Nickerson, Steven Skiena	Attention and Communication: Decision Scenarios for Teleoperating Robots.	HICSS	2005	DBLP DOI BibTeX RDF
21	Dan R. Olsen, Stephen Bart Wood, Jonathan Turner	Metrics for Human Driving of Multiple Robots.	ICRA	2004	DBLP DOI BibTeX RDF
21	Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak	Clustering based acyclic multi-way partitioning.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	multi-way, clustering, CAD, partitioning, acyclic
21	Hirendu Vaishnav, Massoud Pedram	Alphabetic trees-theory and applications in layout-driven logicsynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
21	Colin D. Walter	Faster Modular Multiplication by Operand Scaling.	CRYPTO	1991	DBLP DOI BibTeX RDF	Fast Computer Arithmetic, Digital Arithmetic Methods, RSA Algorithm, Cryptography, Modular Multiplication
21	Zhicheng Wang, Peter M. Maurer	LECSIM: A Levelized Event Driven Compiled Logic Simulation.	DAC	1990	DBLP DOI BibTeX RDF
21	Zhe Yu, Yuhua Liang, Haotian Lan, Li Chen, Jiajun Song, Shida Song, Zhangming Zhu	A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
21		Erratum:Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package [IEICE Electronics Express Vol. 19 (2022) No. 14 pp. 20220122].	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
21	Chi-Wei Wang, Che-Pei Chang, Chang-Chun Lee	Demonstration on Warpage Estimation Approach Utilized in Fan-Out Panel-Level Packaging Enabled by Multi-Scale Process-Oriented Simulation.	IRPS	2023	DBLP DOI BibTeX RDF
21	Hirotaka Oshima, Takashi Kan, Hideaki Tanaka, Hidenori Takahashi, Katsuyuki Utaka, Masatoshi Suzuki	Low Loss Fan-Out Structure for Multimode Waveguide-Based Reservoir Computing.	PSC	2023	DBLP DOI BibTeX RDF
21	Daijiong Chen, Shuangfu Wang, Qifu Wei, Huixiang Huang	Novel Design of an Ultra Compact Software Defined Radio System with High-density Fan-out SiP Technology.	EITCE	2023	DBLP DOI BibTeX RDF
21	Julian Bellavita, Mathias Jacquelin, Esmond G. Ng, Dan Bonachea, Johnny Corbino, Paul H. Hargrove	symPACK: A GPU-Capable Fan-Out Sparse Cholesky Solver.	SC Workshops	2023	DBLP DOI BibTeX RDF
21	Jennifer Volk, George Tzimpragos, Alex Wynn, Evan Golden, Timothy Sherwood	Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions.	CoRR	2022	DBLP DOI BibTeX RDF
21	Ying Chen, Jun Li 0104, Fei Ding, Liqiang Cao	Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
21	Teyuh Chou, Wei Tang 0010, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang	NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Tsubasa Sasaki, Masanori Takahashi, Ryuichi Sugizaki, Yoshihiro Arashitani	4-Core Fan-out with Practical Environmental Performance.	OECC/PSC	2022	DBLP DOI BibTeX RDF
21	Yao Lu, Lixi Wan, Zhiqiang Zhang 0008, Min Su, Weibao Qiu	Design, simulate and performance an embedded fan-out package for 2-D ultrasonic transducer arrays.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
21	Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui	Fan-out of 2 Triangle Shape Spin Wave Logic Gates.	DATE	2021	DBLP DOI BibTeX RDF
21	Pranav Gokhale, Samantha Koretsky, Shilin Huang, Swarnadeep Majumder, Andrew Drucker, Kenneth R. Brown, Frederic T. Chong	Quantum Fan-out: Circuit Optimizations and Technology Modeling.	QCE	2021	DBLP DOI BibTeX RDF
21	Dongfang Pan, Guolong Li, Fangting Miao, Biao Deng, Junying Wei, Daquan Yu, Ming Liu, Lin Cheng 0001	A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density.	ISSCC	2021	DBLP DOI BibTeX RDF
21	Xing Quan, Jiang Luo, Guodong Su, Kai Jing, Jinsong Zhan	A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with Integrated Fan-out Wafer Level Packaging.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
21	Pranav Gokhale, Samantha Koretsky, Shilin Huang, Swarnadeep Majumder, Andrew Drucker, Kenneth R. Brown, Frederic T. Chong	Quantum Fan-out: Circuit Optimizations and Technology Modeling.	CoRR	2020	DBLP BibTeX RDF