Search results for "Full-scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
79	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
78	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Full Scan Embedded Cores.	FTCS	1999	DBLP DOI BibTeX RDF	test generation, design-for-testability, fault simulation, embedded cores, full scan
73	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
73	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design methodology.	ICCAD	1995	DBLP DOI BibTeX RDF	Testing, DFT, Scan design
73	Nicola Nicolici, Bashir M. Al-Hashimi	Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.	DATE	2000	DBLP DOI BibTeX RDF
68	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	On reducing test application time for scan circuits using limited scan operations and transfer sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
68	Dong Xiang, Kaiwei Li, Hideo Fujiwara	Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
66	Soo Young Lee, Kewal K. Saluja	Test application time reduction for sequential circuits with scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
61	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
58	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
58	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
52	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
51	Xiaoding Chen, Michael S. Hsiao	An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
48	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
48	Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li 0036, Krishnendu Chakrabarty	Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
47	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
47	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
46	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	Full Scan Fault Coverage With Partial Scan.	DATE	1999	DBLP DOI BibTeX RDF
46	Seongmoon Wang, Sandeep K. Gupta 0001	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
46	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik	On improving test quality of scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
44	Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa	A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
44	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
43	Zhen Chen, Dong Xiang, Boxue Yin	A power-effective scan architecture using scan flip-flops clustering and post-generation filling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
43	Kohei Miyase, Seiji Kajihara	Optimal Scan Tree Construction with Test Vector Modification for Test Compression.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
43	Ranganathan Sankaralingam, Nur A. Touba	Controlling Peak Power During Scan Testing.	VTS	2002	DBLP DOI BibTeX RDF
43	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee	Test-point insertion: scan paths through functional logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
41	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
41	Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.	FPL	2001	DBLP DOI BibTeX RDF
41	Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta	An RTL methodology to enable low overhead combinational testing.	ED&TC	1997	DBLP DOI BibTeX RDF
39	Irith Pomeranz, Sudhakar M. Reddy	On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
39	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
38	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.	VTS	2008	DBLP DOI BibTeX RDF	Faults in scan cells, stuck-at and stuck-on faults
38	Mehdi Salmani Jelodar, Kiarash Mizanian	Power Aware Scan-Based Testing using Genetic Algorithm.	CCECE	2006	DBLP DOI BibTeX RDF
38	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
38	Prab Varma, Tushar Gheewala	The economics of scan-path design for testability.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
36	Dhiraj K. Pradhan, Jayashree Saxena	A novel scheme to reduce test application time in circuits with full scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
36	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
36	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
34	Irith Pomeranz, Sudhakar M. Reddy	Functional Test Generation for Full Scan Circuits.	DATE	2000	DBLP DOI BibTeX RDF
33	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
33	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.	ISQED	2004	DBLP DOI BibTeX RDF
33	Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy	Synthesis of Scan Chains for Netlist Descriptions at RT-Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	scan synthesis, design for testability (DFT), register transfer level (RTL)
33	Ranganathan Sankaralingam, Nur A. Touba	Inserting Test Points to Control Peak Power During Scan Testing.	DFT	2002	DBLP DOI BibTeX RDF
33	Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya	Reducing Power Dissipation during Test Using Scan Chain Disable.	VTS	2001	DBLP DOI BibTeX RDF
33	Robert B. Norwood, Edward J. McCluskey	High-Level Synthesis for Orthogonal Sca.	VTS	1997	DBLP DOI BibTeX RDF
31	Tinne De Laet, Ruben Smits, Joris De Schutter, Herman Bruyninckx	Adaptive Full Scan Model for Range Finders in Dynamic Environments.	ISER	2008	DBLP DOI BibTeX RDF
31	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
31	Ilker Hamzaoglu, Janak H. Patel	Compact two-pattern test set generation for combinational and full scan circuits.	ITC	1998	DBLP DOI BibTeX RDF
31	Scott Davidson 0001	What's the problem?	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	full-scan test, design for testability, delay test, defects, IC
30	Dilip P. Vasudevan, Aristides Efthymiou	A Partial Scan Based Test Generation for Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
30	Jing Wang, Shengbing Zhang, Zhang Meng	Testing of a 32-bit High Performance Embedded Microprocessor.	SIES	2007	DBLP DOI BibTeX RDF
28	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
28	Yu Hu 0001, Xiaowei Li 0001, Huawei Li 0001, Xiaoqing Wen	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.	PRDC	2005	DBLP DOI BibTeX RDF
26	Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff	Synchronous Full-Scan for Asynchronous Handshake Circuits.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	L1L2*, DFT, asynchronous circuits, scan design, LSSD
26	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	ETS	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
26	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.	VLSI Design	2003	DBLP DOI BibTeX RDF
26	Kwang-Ting Cheng, Chih-Jen Lin	Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST.	ITC	1995	DBLP DOI BibTeX RDF
25	Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng	A Test Synthesis Approach to Reducing BALLAST DFT Overhead.	DAC	1997	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.	DATE	2005	DBLP DOI BibTeX RDF
24	Yu-Chiun Lin, Shi-Yu Huang	Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
24	Aiman El-Maleh, Ali Al-Suwaiyan	An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits.	VTS	2002	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	Output-Dependent Diagnostic Test Generation.	VLSI Design	2010	DBLP DOI BibTeX RDF	diagnostic test generation, stuck-at faults, full-scan circuits
23	Scott Davidson 0001	The commonality of vector generation techniques.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	output compression, non-fault-directed test, semi-fault-directed test, ATPG, test compression, full scan, vector generation, logic BIST
23	Irith Pomeranz, Sudhakar M. Reddy	Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.	VTS	2008	DBLP DOI BibTeX RDF	functional broadside tests, test generation, transition faults, reachable states, full-scan circuits
23	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
23	Yong-sheng Cheng, Zhiqiang You, Jishun Kuang	Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.	DELTA	2008	DBLP DOI BibTeX RDF	full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
23	Wang-Dauh Tseng	Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	transition density, switching activity during test, clique, low power testing, full scan
23	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	An evolutionary algorithm for reducing integrated-circuit test application time.	SAC	2002	DBLP DOI BibTeX RDF	interleaved-scan, test, evolutionary algorithm, computer aided design, full-scan
23	Madhu K. Iyer, Kwang-Ting Cheng	Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs.	VTS	2002	DBLP DOI BibTeX RDF
23	Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal	A partition and resynthesis approach to testable design of large circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
23	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
23	Irith Pomeranz, Sudhakar M. Reddy	Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
23	Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho	Test Power Reduction with Multiple Capture Orders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
23	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
23	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial-scan delay fault testing of asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
23	Arun Balakrishnan, Srimat T. Chakradhar	Sequential Circuits with combinational Test Generation Complexity.	VLSI Design	1996	DBLP DOI BibTeX RDF
23	Ajay Khoche, Erik Brunvand	Testing self-timed circuits using partial scan.	ASYNC	1995	DBLP DOI BibTeX RDF	sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
20	Tsung-Chu Huang, Kuen-Jong Lee	Reduction of power consumption in scan-based circuits during testapplication by an input control technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
20	Seongmoon Wang, Sandeep K. Gupta 0001	ATPG for Heat Dissipation Minimization During Scan Testing.	DAC	1997	DBLP DOI BibTeX RDF
20	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel	Sequential circuit testability enhancement using a nonscan approach.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
18	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Themistoklis Haniotakis, Spyros Tragoudas, G. Pani	Reduced Test Application Time Based on Reachability Analysis.	ISQED	2005	DBLP DOI BibTeX RDF
18	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
18	Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang	A Study on Insuring the Full Reliability of Finite State Machine.	ICCSA (2)	2003	DBLP DOI BibTeX RDF
18	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka	A SoC Test Strategy Based on a Non-Scan DFT Method.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	non-scan DFT, high level design and test, SoC test
18	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
18	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
16	Qidong Wang, Aijiao Cui, Gang Qu 0001	Identification of Counter Registers through Full Scan Chain.	ITC-Asia	2021	DBLP DOI BibTeX RDF
16	Chengkang He, Aijiao Cui, Chip-Hong Chang	Identification of State Registers of FSM Through Full Scan by Data Analytics.	AsianHOST	2019	DBLP DOI BibTeX RDF
16	Sylwester Milewski, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada	Full-scan LBIST with capture-per-cycle hybrid test points.	ITC	2017	DBLP DOI BibTeX RDF
16	Tinne De Laet, Joris De Schutter, Herman Bruyninckx	A Rigorously Bayesian Beam Model and an Adaptive Full Scan Model for Range Finders in Dynamic Environments.	CoRR	2014	DBLP BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	Static test compaction for diagnostic test sets of full-scan circuits.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
16	Irith Pomeranz, Sudhakar M. Reddy	On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
16	Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
16	Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Tinne De Laet, Joris De Schutter, Herman Bruyninckx	A Rigorously Bayesian Beam Model and an Adaptive Full Scan Model for Range Finders in Dynamic Environments.	J. Artif. Intell. Res.	2008	DBLP DOI BibTeX RDF