Search results for "IEEE-1149.1"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Bill Eklow, Carl Barnhart, Mike Ricchetti, Terry Borroz	IEEE 1149.6 - A Practical Perspective.	ITC	2003	DBLP DOI BibTeX RDF
104	Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu	Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
96	Bulent I. Dervisoglu, Mike Ricchetti, William Eklow	Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.	ITC	1998	DBLP DOI BibTeX RDF
79	Chouki Aktouf, Chantal Robach, A. Marinescu, Guy Mazaré	An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	routing test, IEEE 1149.1, built-in self-test, diagnosis, MIMD architectures
74	Rakesh N. Joshi, Kenneth L. Williams, Lee Whetsel	Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices.	ITC	2003	DBLP DOI BibTeX RDF
68	Bart Vermeulen, Tom Waayers, Sjaak Bakker	Multi-TAP Controller Architecture for Digital System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP
64	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
64	Dilip K. Bhavsar	Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
64	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
59	Kuen-Jong Lee, Cheng-I Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
58	Francisco R. Fernandes, Ricardo J. Machado 0001, José M. Ferreira 0001, Manuel G. Gericota	Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports.	IOLTS	2012	DBLP DOI BibTeX RDF
53	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
51	Jose M. M. Ferreira, Manuel G. O. Gericota, Antonio M. Cardoso	An integrated framework to support remote IEEE 1149.1 / 1149.4 design for test experiments.	Int. J. Online Eng.	2006	DBLP BibTeX RDF
50	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	An Embedded IDDQ Testing Architecture and Technique.	ISQED	2003	DBLP DOI BibTeX RDF	IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
50	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
50	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
50	Hong Hao, Kanti Bhabuthmal	Clock controller design in SuperSPARC II microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
47	Subhasish Mitra, Edward J. McCluskey, Samy Makar	Design for Testability and Testing of IEEE 1149.1 Tap Controller.	VTS	2002	DBLP DOI BibTeX RDF
47	Dave Stang, Ramaswami Dandapani	An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements.	ITC	2002	DBLP DOI BibTeX RDF
47	Sungju Park, Taehyung Kim	A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects.	DATE	2000	DBLP DOI BibTeX RDF
47	Najmi T. Jarwala	Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	module test, design-for-testability, boundary-scan
45	Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani	A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic.	ITC	2003	DBLP DOI BibTeX RDF
44	Bill Eklow, Ben Bennetts	New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).	ETS	2006	DBLP DOI BibTeX RDF
40	Bill Eklow, Carl Barnhart, Kenneth P. Parker	IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.	ITC	2002	DBLP DOI BibTeX RDF
36	Bradford G. Van Treuren, José M. Miranda	Embedded Boundary Scan.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
36	Tom Waayers	An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.	ITC	2003	DBLP DOI BibTeX RDF
36	Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora	A Structured Graphical Tool for Analyzing Boundary Scan Violations.	ITC	2002	DBLP DOI BibTeX RDF
36	Colin M. Maunder	A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
36	Dilip K. Bhavsar	Testing Interconnections to Static RAMs.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
35	Reza Nourmandi-Pour, Nafiseh Mousavian, Ahmad Khadem-Zadeh	BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
35	Bulent I. Dervisoglu	A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers.	DAC	2001	DBLP DOI BibTeX RDF
32	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang	Using a single input to support multiple scan chains.	ICCAD	1998	DBLP DOI BibTeX RDF	boundary scan (IEEE 1149.1) and test compaction, test generation, design for testability, scan based design
31	W. David Ballew, Lauren M. Streb	Board-level boundary scan: regaining observability with an additional IC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	Don Sterba, Andy Halliday, Don McClean	ATPG and diagnostics for boards implementing boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	1149.1, ATPG, diagnostics, boundary scan, JTAG
30	Michael Higgins, Ciaran MacNamee, Brendan Mullane	SoCECT: System on Chip Embedded Core Test.	DDECS	2008	DBLP DOI BibTeX RDF
29	Sebastian Huhn 0001, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler	Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.	DATE	2017	DBLP DOI BibTeX RDF
29	André V. Fidalgo, Andre Couto, Manuel C. Felgueiras, Gustavo R. Alves	Low cost boundary scan controller for didactic applications (IEEE 1149.1).	exp.at	2015	DBLP DOI BibTeX RDF
29	Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume	Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.	3DIC	2011	DBLP DOI BibTeX RDF
29	Tsung-Yen Tsai, Gordon W. Roberts	Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus.	CICC	2011	DBLP DOI BibTeX RDF
29	Reza Nourmandi-Pour, Ahmad Khademzadeh, Amir Masoud Rahmani	An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
29	C. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill	Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins.	ITC	2010	DBLP DOI BibTeX RDF
29	Dave Bonnett	IEEE 1149.1- The Internet of Test.	LATW	2001	DBLP BibTeX RDF
29	Steven F. Oakland	Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits.	ITC	2000	DBLP DOI BibTeX RDF
29	Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
29	Yuejian Wu, Paul Soong	Interconnect delay fault testing with IEEE 1149.1.	ITC	1999	DBLP DOI BibTeX RDF
29	Dilip Bhavsar	A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access.	VLSI Design	1998	DBLP DOI BibTeX RDF
29	Ken Posse	A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	fault diagnosis, Boundary-Scan, Multichip Module, MCM, interconnect testing, manufacturing defects
29	Lee Whetsel	An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores.	ITC	1997	DBLP DOI BibTeX RDF
29	Chouki Aktouf, Chantal Robach, A. Marinescu	A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1.	ITC	1995	DBLP DOI BibTeX RDF
29	John Andrews	Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test Programs.	ITC	1994	DBLP DOI BibTeX RDF
29	Lee Whetsel	An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures.	ITC	1994	DBLP DOI BibTeX RDF
29	Najmi T. Jarwala	Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules.	ITC	1994	DBLP DOI BibTeX RDF
29	Alfred L. Crouch, Rick Ramus, Colin M. Maunder	Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution.	ITC	1994	DBLP DOI BibTeX RDF
29	John Andrews	Using SCANTM Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test Bus.	ITC	1994	DBLP DOI BibTeX RDF
29	Lee Whetsel	An IEEE 1149.1 based voltmeter/oscilloscope in a chip.	VTS	1993	DBLP DOI BibTeX RDF
29	Mick Tegethoff	IEEE 1149.1: How to Justify Implementation.	ITC	1993	DBLP BibTeX RDF
29	Wayne T. Daniel	IEEE 1149.1 Growing Pains.	ITC	1993	DBLP BibTeX RDF
29	Mark Royals, Tassos Markas, Nick Kanopoulos	A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
29	Robert C. Zak Jr., Jeffrey V. Hill	An IEEE 1149.1 Compliant Testability Architecture with Internal Scan.	ICCD	1992	DBLP DOI BibTeX RDF
29	John Andrews	IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic.	ITC	1992	DBLP DOI BibTeX RDF
29	Barry Caldwell, Tom Langford	Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study.	ITC	1992	DBLP DOI BibTeX RDF
29	Wayne T. Daniel	Design Verification of a High Density Computer Using IEEE 1149.1.	ITC	1992	DBLP DOI BibTeX RDF
29	Lee Whetsel	An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip.	ITC	1991	DBLP DOI BibTeX RDF
29	David L. Landis, Padmaraj Singh	Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration.	ITC	1990	DBLP DOI BibTeX RDF
22	Paolo Bernardi, Matteo Sonza Reorda	An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers.	DATE	2008	DBLP DOI BibTeX RDF
22	Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park	An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
22	Bart Vermeulen, Tom Waayers, Sjaak Bakker	EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.	ITC	2002	DBLP DOI BibTeX RDF
22	T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
18	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
18	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
18	Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek	Communication-Centric SoC Debug Using Transactions.	ETS	2007	DBLP DOI BibTeX RDF
18	MoonJoon Kim, JeongMin Lee, WonGi Hong, Hoon Chang	A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
18	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	Equivalent IDDQ Tests for Systems with Regulated Power Supply.	DFT	2006	DBLP DOI BibTeX RDF
18	Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard	Testing High-Speed IO Links Using On-Die Circuitry.	VLSI Design	2006	DBLP DOI BibTeX RDF	link characterization, on-die oscilloscope, BER, register file, JTAG, IO
18	Mário Zenha Rela, João Carlos Cunha, Carlos Bruno Silva, Luís Ferreira da Silva	On the Effects of Errors During Boot.	LADC	2005	DBLP DOI BibTeX RDF	fault-tolerance, embedded systems, fault-injection, boundary-scan, dependability evaluation
18	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IEEE P1500, diagnosis, Hough transform, embedded memories
18	Rawat Siripokarpirom, Friedrich Mayer-Lindenberg	Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
18	Olivier Duval, L.-P. Lafrance, Yvon Savaria, Patrick Desjardins	An Integrated Test Platform for Nanostructure Electrical Characterization.	ICMENS	2004	DBLP DOI BibTeX RDF
18	Charles Njinda	A Hierarchical DFT Architecture for Chip, Board and System Test/Debug.	ITC	2004	DBLP DOI BibTeX RDF
18	Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung	Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.	ITC	2004	DBLP DOI BibTeX RDF
18	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity.	ICCD	2003	DBLP DOI BibTeX RDF
18	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Testing SoC Interconnects for Signal Integrity Using Boundary Scan.	VTS	2003	DBLP DOI BibTeX RDF	Integrity Loss Sensor, System-on-Chip Interconnects, Data Compression, Boundary Scan, Signal Integrity
18	Lee Whetsel	Adapting JTAG for AC Interconnect Testing.	ITC	2003	DBLP DOI BibTeX RDF
18	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
18	Jaehoon Song, Sungju Park	A Simple Wrapped Core Linking Module for SoC Test Access.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
18	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF
18	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	MTDT	2002	DBLP DOI BibTeX RDF
18	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
18	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	IOLTW	2002	DBLP DOI BibTeX RDF
18	Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao	Reusable embedded in-circuit emulator.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira 0001	DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs.	IOLTW	2001	DBLP DOI BibTeX RDF
18	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
18	Gustavo R. Alves, José Manuel Martins Ferreira	From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1.	VTS	1999	DBLP DOI BibTeX RDF
18	Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud	Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access.	VTS	1999	DBLP DOI BibTeX RDF
18	Frank W. Angelotti	Generating interconnect models from prototype hardware.	ITC	1998	DBLP DOI BibTeX RDF
18	Joel A. Jorgenson, Russell J. Wagner	Design-For-Test in a Multiple Substrate Multichip Module.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	Multichip Module (MCM) Test, Known-Good Die (KGD), Ball Grid Array (BGA), Built-In-Self-Test (BIST), boundary-scan
18	José M. Miranda	A BIST and Boundary-Scan Economics Framework.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
18	Kanad Chakraborty, Pinaki Mazumder	A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.	ED&TC	1997	DBLP DOI BibTeX RDF
18	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
18	Mick Tegethoff, Tom Chen 0001	Sensitivity Analysis of Critical Parameters in Board Test.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF