Search results for "Inductance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Kaveh Shakeri, James D. Meindl	Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
110	Santosh Shah, Arani Sinha, Li Song, Narain D. Arora	On-Chip Inductance in X Architecture Enabled Design.	ISQED	2007	DBLP DOI BibTeX RDF
110	N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell	The Impact of Inductance on Transients Affecting Gate Oxide Reliability.	VLSI Design	2005	DBLP DOI BibTeX RDF
105	Takashi Sato, Hiroo Masuda	Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.	ISQED	2003	DBLP DOI BibTeX RDF
100	Andrey V. Mezhiba, Eby G. Friedman	Properties of on-chip inductive current loops.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	loop inductance, inductance, inductive coupling
98	Andrey V. Mezhiba, Eby G. Friedman	Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits.	ISQED	2002	DBLP DOI BibTeX RDF	mutual inductance, partial inductance, inductance, power grids, power distribution networks
89	Hemant Mahawar, Vivek Sarin	Parallel algorithms for inductance extraction of VLSI circuits.	IPDPS	2006	DBLP DOI BibTeX RDF
89	Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi	Inductance model and analysis methodology for high-speed on-chip interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
89	Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai	KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect.	ASP-DAC	2001	DBLP DOI BibTeX RDF
89	Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada	Computational Cost Reduction in Extracting Inductance.	ISQED	2001	DBLP DOI BibTeX RDF
89	Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw	On-chip inductance modeling and analysis.	DAC	2000	DBLP DOI BibTeX RDF
84	Mosin Mondal, Yehia Massoud	Accurate Loop Self Inductance Bound for Efficient Inductance Screening.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
79	Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester	Optimal Inductance for On-chip RLC Interconnections.	ICCD	2003	DBLP DOI BibTeX RDF
79	Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi	Equipotential shells for efficient inductance extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
79	David T. Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang	On-chip inductance modeling.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
76	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
76	Shen Lin, Norman Chang, O. Sam Nakagawa	Quick On-Chip Self- and Mutual-Inductance Screen.	ISQED	2000	DBLP DOI BibTeX RDF	inductance screening, significant frequency, inductive coupling and inductive modeling, signal integrity
74	Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal	Inductance Characterization of Small Interconnects Using Test-Signal Method.	VLSI Design	2000	DBLP DOI BibTeX RDF	Test-Signal Injection Method, Differential Circuit, Short Interconnects, Self and Mutual-Inductance, High Frequency Test Signal, Displacement Current, Lumped Package Models, Inductance, Characterization, Transmission Lines, Capacitance, Substrate
68	Abinash Roy, Masud H. Chowdhury	Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.	APCCAS	2006	DBLP DOI BibTeX RDF
68	T. Chen	On the impact of on-chip inductance on signal nets under the influence of power grid noise.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
68	Woo Hyung Lee, Sanjay Pant, David T. Blaauw	Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids.	ISQED	2004	DBLP DOI BibTeX RDF
68	Haitian Hu, Sachin S. Sapatnekar	Efficient inductance extraction using circuit-aware techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
68	Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, Howard H. Smith	A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
68	Kaustav Banerjee, Amit Mehrotra	Analysis of on-chip inductance effects for distributed RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
68	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar	A precorrected-FFT method for simulating on-chip inductance.	ICCAD	2002	DBLP DOI BibTeX RDF
68	Yehea I. Ismail, Eby G. Friedman	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
66	Rafael Escovar, Salvador Ortiz 0002, Roberto Suaya	Mutual inductance extraction and the dipole approximation.	ISPD	2004	DBLP DOI BibTeX RDF	mutual coupling, inductance, approximation methods, parasitic extraction, electromagnetic fields
66	Hemant Mahawar, Vivek Sarin, Weiping Shi	Fast Inductance Extraction of Large VLSI Circuits.	IPDPS	2002	DBLP DOI BibTeX RDF	Inductance extraction, VLSI, parallel computing, iterative methods, preconditioning
66	Tao Lin, Michael W. Beattie, Lawrence T. Pileggi	On the efficacy of simplified 2D on-chip inductance models.	DAC	2002	DBLP DOI BibTeX RDF	PEEC, on-chip inductance, sparsified model
64	Byron Krauter, Lawrence T. Pileggi	Generating sparse partial inductance matrices with guaranteed stability.	ICCAD	1995	DBLP DOI BibTeX RDF	partial inductance, partial inductance matrices, magnetic vector potential
58	K. C. Narasimhamurthy, Roy P. Paily	Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects.	VLSI Design	2009	DBLP DOI BibTeX RDF
58	Yuichi Tanji, Takayuki Watanabe, Hideki Asai	Generating stable and sparse reluctance/inductance matrix under insufficient conditions.	ASP-DAC	2008	DBLP DOI BibTeX RDF
58	Dipanjan Gope, Albert E. Ruehli, Vikram Jandhyala	Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
58	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail	Including inductance in static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
58	Mustafa Acar, Anne-Johan Annema, Bram Nauta	Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance.	ISCAS	2007	DBLP DOI BibTeX RDF
58	Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai	Inductance extraction for general interconnect structures.	ISCAS	2006	DBLP DOI BibTeX RDF
58	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
58	Rafael Escovar, Salvador Ortiz 0002, Roberto Suaya	An improved long distance treatment for mutual inductance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
58	Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong	Compact and stable modeling of partial inductance and reluctance matrices.	ASP-DAC	2005	DBLP DOI BibTeX RDF
58	Navin Srivastava, Xiaoning Qi, Kaustav Banerjee	Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
58	Soyoung Kim, Yehia Massoud, S. Simon Wong	On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond.	ISQED	2003	DBLP DOI BibTeX RDF
58	S. Simon Wong, C. Patrick Yue, Richard Chang 0003, So-Young Kim, Bendik Kleveland, Frank O'Mahony	On-Chip Interconnect Inductance - Friend or Foe (Invited).	ISQED	2003	DBLP DOI BibTeX RDF
58	Yehia Massoud, Jacob K. White 0001	Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
58	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Exploiting the on-chip inductance in high-speed clock distribution networks.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
58	A. J. Dammers, N. P. van der Meijs	Virtual screening: a step towards a sparse partial inductance matrix.	ICCAD	1999	DBLP DOI BibTeX RDF
58	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Inductance Effects in RLC Trees.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
56	Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, David Smart	A fast block structure preserving model order reduction for inverse inductance circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	inductance and interconnect modeling, model order reduction
56	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
56	Satrajit Gupta, Lawrence T. Pileggi	CHIME: coupled hierarchical inductance model evaluation.	DAC	2004	DBLP DOI BibTeX RDF	inductance modeling, circuit simulation
56	Hemant Mahawar, Vivek Sarin, Weiping Shi	A solenoidal basis method for efficient inductance extraction.	DAC	2002	DBLP DOI BibTeX RDF	inductance extraction, solenoidal basis, interconnect, iterative methods, preconditioning
52	Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez	Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology.	SBCCI	2009	DBLP DOI BibTeX RDF	cross inductors, rectangular inductors, RF CMOS
52	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li 0001, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
52	Laureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret	Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation.	ISQED	2006	DBLP DOI BibTeX RDF
50	Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter	Spatially distributed 3D circuit models.	DAC	2005	DBLP DOI BibTeX RDF	boundary element method (BEM), distributed circuit models, inverse inductance, capacitance
47	Abinash Roy, Masud H. Chowdhury	Global Interconnect Optimization in the Presence of On-chip Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
47	Denis Deschacht	DSM interconnects: importance of inductance effects and corresponding range of length.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
47	Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh	Stable and compact inductance modeling of 3-D interconnect structures.	ICCAD	2006	DBLP DOI BibTeX RDF
47	Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis	An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain.	DATE	2004	DBLP DOI BibTeX RDF
47	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar	Fast on-chip inductance simulation using a precorrected-FFT method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
47	Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen	INDUCTWISE: inductance-wise interconnect simulator and extractor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
47	Yehea I. Ismail	On-chip inductance cons and pros.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
47	Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen	INDUCTWISE: inductance-wise interconnect simulator and extractor.	ICCAD	2002	DBLP DOI BibTeX RDF
47	Haitian Hu, Sachin S. Sapatnekar	Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques.	ICCD	2002	DBLP DOI BibTeX RDF
47	Kaustav Banerjee, Amit Mehrotra	Inductance Aware Interconnect Scaling.	ISQED	2002	DBLP DOI BibTeX RDF
47	Tom Chen 0001	Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology.	ISQED	2001	DBLP DOI BibTeX RDF
47	Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He 0001	Clocktree RLC Extraction with Efficient Inductance Modeling.	DATE	2000	DBLP DOI BibTeX RDF
47	Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob K. White 0001	Layout Techniques for Minimizing On-Chip Interconnect Self Inductance.	DAC	1998	DBLP DOI BibTeX RDF
47	Zhijiang He, Mustafa Celik, Lawrence T. Pileggi	SPIE: Sparse Partial Inductance Extraction.	DAC	1997	DBLP DOI BibTeX RDF
45	Alexandre Nentchev, Siegfried Selberherr	Three-dimensional on-chip inductance and resistance extraction.	SBCCI	2007	DBLP DOI BibTeX RDF	on-chip resistance and inductance extraction, FEM
45	Liu Yang, Xiaobo Guo, Zeyi Wang	An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF	Inductance extraction, Multiple right-hand sides, Multipole method, PEEC
45	Hemant Mahawar, Vivek Sarin	Parallel Software for Inductance Extraction.	ICPP	2004	DBLP DOI BibTeX RDF	Inductance extraction, Mixed mode parallelization, Parallel computing, Iterative methods, Preconditioning
45	Yuichi Tanji, Hideki Asai	Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.	DAC	2004	DBLP DOI BibTeX RDF	RLC distributed interconnects, inductance effects
42	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
42	Clement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen	Frequency-dependent reluctance extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
42	Andrey V. Mezhiba, Eby G. Friedman	Inductive properties of high-performance power distribution grids.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
39	Yu Du, Wayne Dai	Partial reluctance based circuit simulation is efficient and stable.	ASP-DAC	2005	DBLP DOI BibTeX RDF	magnetic field, partial reluctance, vector potential, inductance, extraction, shielding
39	Shaolei Quan, Chin-Long Wey	A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CMOS, inductance, RF, LNA
39	Mohamed A. Elgamel, Magdy A. Bayoumi	Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction.	SBCCI	2003	DBLP DOI BibTeX RDF	Shield insertion, Algorithms, Noise, Inductance, DSM
37	Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan	A fast band-matching technique for interconnect inductance modeling.	ICCAD	2007	DBLP DOI BibTeX RDF
37	Changhao Yan, Wenjian Yu, Zeyi Wang	Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.	ASP-DAC	2006	DBLP DOI BibTeX RDF
37	Qing Wu, Subhasis Nandi	A Novel Approach to Calculate Squirrel Cage Induction Motor Rotor Leakage Inductance.	CCECE	2006	DBLP DOI BibTeX RDF
37	Shahram Minaei, Erkan Yüce, Oguzhan Cicekoglu	Lossless Active Floating Inductance Simulator.	DELTA	2006	DBLP DOI BibTeX RDF
37	Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo	A 5.25 GHz CMOS even harmonic mixer with an enhancing inductance.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
37	Hemant Mahawar, Vivek Sarin, Ananth Grama	Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction.	HiPC	2004	DBLP DOI BibTeX RDF
37	Bruno Estibals, Corinne Alonso, Franck Carcenac, Alain Salles, Laurent Malaquin, Christophe Vieu	Design and realisation of a nano-inductance for integrated power converters.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
37	Yu Cao 0001, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
37	Dipak Sitaram, Yu Zheng, Kenneth L. Shepard	Implicit treatment of substrate and power-ground losses in return-limited inductance extraction.	ICCAD	2002	DBLP DOI BibTeX RDF
37	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
37	Takeshi Sakurada, Oichi Atoda, Masaki Nakagawa, Kiyoshi Kiyokawa	Algorithm Design and Prototype of a Low-Cost Electromagnetic Inductance Real-Time 6D-Tracker.	ICOIN	2001	DBLP DOI BibTeX RDF	magnetic sensor, 3-D measurement, 6D tracker, Motion capture
37	Yu Cao 0001, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.	ISQED	2001	DBLP DOI BibTeX RDF
37	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of merit to characterize the importance of on-chip inductance.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
37	Youxin Gao, Martin D. F. Wong	Wire-sizing optimization with inductance consideration using transmission-line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
37	Ichirou Oota, Noriaki Hara, Fumio Ueno	Influence of parasitic inductance on serial fixed type switched-capacitor transformer.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
37	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of Merit to Characterize the Importance of On-Chip Inductance.	DAC	1998	DBLP DOI BibTeX RDF
35	Michael W. Beattie, Lawrence T. Pileggi	IC Analyses Including Extracted Inductance Models.	DAC	1999	DBLP DOI BibTeX RDF	interconnect, inductance, model order reduction
35	Shannon V. Morton	On-Chip Inductance Issues in Multiconductor Systems.	DAC	1999	DBLP DOI BibTeX RDF	alpha microprocessor, cross-talk, interconnect, noise, inductance, transmission line, capacitance, resistance, buses, semiconductor, RLC
31	Sushanta K. Mandal, Shamik Sural, Amit Patra	ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Ioannis Savidis, Eby G. Friedman	Electrical modeling and characterization of 3-D vias.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Wei Liu, L. Q. Wong, Ming Mao Wong	Simulation and design for 3D RFID application.	ETFA	2008	DBLP DOI BibTeX RDF
31	Mikhail Popovich, Eby G. Friedman	Decoupling capacitors for multi-voltage power distribution systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF