Search results for "Instructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
92	A. F. R. Brown	Language Translation.	J. ACM	1958	DBLP DOI BibTeX RDF
78	Julie Heiser, Doantam Phan, Maneesh Agrawala, Barbara Tversky, Pat Hanrahan	Identification and validation of cognitive design principles for automated generation of assembly instructions.	AVI	2004	DBLP DOI BibTeX RDF	assembly instructions, visual instructions, diagrams, design principles, spatial ability
78	A. P. Wim Böhm, John R. Gurd	Iterative Instructions in the Manchester Dataflow Computer.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration
77	Shay Gueron	Intel's New AES Instructions for Enhanced Performance and Security.	FSE	2009	DBLP DOI BibTeX RDF	new instructions set, computer architecture, Advanced Encryption Standard
77	Sumeet Kumar, Aneesh Aggarwal	Self-checking instructions: reducing instruction redundancy for concurrent error detection.	PACT	2006	DBLP DOI BibTeX RDF	RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures
74	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa	Pack instruction generation for media pUsing multi-valued decision diagram.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-valued decision diagram, SIMD instructions
67	Daniel Spelmezan, Mareike Jacobs, Anke Hilgers, Jan O. Borchers	Tactile motion instructions for physical activities.	CHI	2009	DBLP DOI BibTeX RDF	real-time instructions, sports training, vibrotactile feedack, physical activities, motor skills
63	Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder	Reducing code size with echo instructions.	CASES	2003	DBLP DOI BibTeX RDF	code size optimization, echo instructions, compression
61	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Limitations of special-purpose instructions for similarity measurements in media SIMD extensions.	CASES	2006	DBLP DOI BibTeX RDF	sub-word parallelism, similarity measurements, SIMD
58	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy	Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.	ASPLOS	2006	DBLP DOI BibTeX RDF	redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
57	Sangho Ha, Sangyong Han, Heunghwan Kim	Partitioning a lenient parallel language into sequential threads.	HICSS (2)	1995	DBLP DOI BibTeX RDF	lenient parallel language, language partitioning, sequential threads, multithreaded architecture performance, large-scale parallel system, split-phase memory operations, fast context switching, multithreaded code quality, enhanced thread formation scheme, Id/sup -/, long latency instructions, multiple switches, generalized switch-and-merge, thread merging, redundant arc elimination, thread precedence relations, control instructions, DAVRID multithreaded architecture, simulation, graph theory, parallel architectures, graph partitioning, switching, merging, parallel languages, large-scale systems, program control structures, branch instructions
56	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP DOI BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
55	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
54	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
53	Enric Morancho, José María Llabería, Àngel Olivé	Recovery Mechanism for Latency Misprediction.	IEEE PACT	2001	DBLP DOI BibTeX RDF
53	Arvind Krishnaswamy, Rajiv Gupta 0001	Enhancing the performance of 16-bit code using augmenting instructions.	LCTES	2003	DBLP DOI BibTeX RDF	16-bit thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, embedded processor, code size
52	Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing.	MICRO	2005	DBLP DOI BibTeX RDF
52	Jingren Zhou, Kenneth A. Ross	Implementing database operations using SIMD instructions.	SIGMOD Conference	2002	DBLP DOI BibTeX RDF
52	David Hovemeyer, William W. Pugh, Jaime Spacco	Atomic Instructions in Java.	ECOOP	2002	DBLP DOI BibTeX RDF
52	Hideo Wada, K. Ishil, Masakazu Fukagawa, H. Murayama, Shun Kawabe	High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system.	ICS	1988	DBLP DOI BibTeX RDF
49	Hui Wang, Rama Sangireddy, Sandeep Baldawa	Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
49	J. Adam Butts, Gurindar S. Sohi	Dynamic dead-instruction detection and elimination.	ASPLOS	2002	DBLP DOI BibTeX RDF
48	Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, Toshio Nakatani	A new idiom recognition framework for exploiting hardware-assist instructions.	ASPLOS	2006	DBLP DOI BibTeX RDF	VMX, hardware-assist instructions, idiom recognition, topological embedding, java, JIT
48	Maneesh Agrawala, Doantam Phan, Julie Heiser, John Haymaker, Jeff Klingner, Pat Hanrahan, Barbara Tversky	Designing effective step-by-step assembly instructions.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	assembly instructions, visualization
47	Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan	MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.	DATE	2004	DBLP DOI BibTeX RDF
44	Vincent J. DiGri, Jane E. King	The Share 709 System: Input-Output Translation.	J. ACM	1959	DBLP DOI BibTeX RDF
42	Aamer Jaleel, Bruce L. Jacob	Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions.	HPCA	2005	DBLP DOI BibTeX RDF
42	Newton Cheung, Sri Parameswaran, Jörg Henkel	A quantitative study and estimation models for extensible instructions in embedded processors.	ICCAD	2004	DBLP DOI BibTeX RDF
42	Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai	A Code Selection Method for SIMD Processors with PACK Instructions.	SCOPES	2003	DBLP DOI BibTeX RDF
42	Ruby B. Lee, A. Murat Fiskiran, Abdulla Bubsha	Multimedia Instructions In IA-64.	ICME	2001	DBLP DOI BibTeX RDF
42	Norman Ramsey, Mary F. Fernandez	Specifying Representations of Machine Instructions.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	encoding, decoding, compiler generation, relocation, object code, machine description, machine code
42	Norman Ramsey	Relocating Machine Instructions by Currying.	PLDI	1996	DBLP DOI BibTeX RDF
42	John G. Cleary, Murray Pearson, Husam Kinawi	The architecture of an optimistic CPU: the WarpEngine.	HICSS (1)	1995	DBLP DOI BibTeX RDF	optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
39	Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería	On reducing misspeculations in a pipelined scheduler.	IPDPS	2009	DBLP DOI BibTeX RDF
39	Rama Sangireddy, Jatan P. Shah	Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
39	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
39	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
39	Alexei Kudriavtsev, Peter M. Kogge	Generation of permutations for SIMD processors.	LCTES	2005	DBLP DOI BibTeX RDF	SIMD, permutations
39	Ching-Wen Chen, Chang-Jung Ku, Chih-Hung Chang	Designing a High Performance and Low Energy-Consuming Embedded System with Considering Code Compressed Environments.	RTCSA	2005	DBLP DOI BibTeX RDF	decompression engine, performance, Embedded system, locality, power consumption, code compress
39	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
39	Jack W. Davidson, David B. Whalley	Ease: An Environment for Architecture Study and Experimentation.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
38	Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke	Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.	CGO	2010	DBLP DOI BibTeX RDF	ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection
38	Roan Boer Rookhuiszen, Mariët Theune	Generating Instructions in a 3D Game Environment: Efficiency or Entertainment?.	INTETAIN	2009	DBLP DOI BibTeX RDF	efficiency vs. entertainment, evaluation, game, instructions, Natural Language Generation, 3D environment
38	Daniel Spelmezan, Anke Hilgers, Jan O. Borchers	A language of tactile motion instructions.	Mobile HCI	2009	DBLP DOI BibTeX RDF	motor skill learning, real-time instructions, sports training, tactile language, physical activities, vibrotactile feedback
38	Luca Chittaro, Daniele Nadalutti	Presenting evacuation instructions on mobile devices by means of location-aware 3D virtual environments.	Mobile HCI	2008	DBLP DOI BibTeX RDF	navigation instructions, mobile devices, RFID, 3D models, emergencies
38	Atsuko K. Yamazaki, Joji Yabutani, Yoko Ebisawa, Satoshi Hori	A Study of Meaning Comprehensibility of Pictograms for Lathe Procedural Instructions.	KES (3)	2007	DBLP DOI BibTeX RDF	manufacturing instructions, communication, comprehensibility, pictogram
38	Xuemeng Zhang, Rongcai Zhao, Jianmin Pang	Semantic Abstraction of IA-64 Multimedia Instructions.	SKG	2006	DBLP DOI BibTeX RDF	multimedia instructions, semantic abstraction, binary translation, IA-64
38	Arvind Krishnaswamy, Rajiv Gupta 0001	Dynamic coalescing for 16-bit instructions.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size
38	Philip Brisk, Jamie Macbeth 0001, Ani Nahapetian, Majid Sarrafzadeh	A dictionary construction technique for code compression systems with echo instructions.	LCTES	2005	DBLP DOI BibTeX RDF	(dictionary) compression, echo instructions, scheduling
38	Zhijie Shi, Ruby B. Lee	Bit Permutation Instructions for Accelerating Software Cryptography.	ASAP	2000	DBLP DOI BibTeX RDF	bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture
37	Yedidya Hilewitz, Ruby B. Lee	Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations
37	Yuto Kawahara, Kazumaro Aoki, Tsuyoshi Takagi	Faster Implementation of eta-T Pairing over GF(3m) Using Minimum Number of Logical Instructions for GF(3)-Addition.	Pairing	2008	DBLP DOI BibTeX RDF	GF(3)-addition, logical instruction, ? T pairing
37	Kai-Florian Richter, Matt Duckham	Simplest Instructions: Finding Easy-to-Describe Routes for Navigation.	GIScience	2008	DBLP DOI BibTeX RDF
37	Pan Yu, Tulika Mitra	Disjoint Pattern Enumeration for Custom Instructions Identification.	FPL	2007	DBLP DOI BibTeX RDF
37	Enric Morancho, José María Llabería, Àngel Olivé	On reducing energy-consumption by late-inserting instructions into the issue queue.	ISLPED	2007	DBLP DOI BibTeX RDF	L2 hit-miss prediction, memory-latency tolerant processors, energy consumption
37	Yedidya Hilewitz, Ruby B. Lee	Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions.	ASAP	2006	DBLP DOI BibTeX RDF
37	Sung Dae Kim, Jung Hoo Lee, J. M. Yang, Myung Hoon Sunwoo, Seung Keun Oh	Novel instructions and their hardware architecture for video signal processing.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
37	Jinson Koppanalil, Eric Rotenberg	A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture
37	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	ACM Trans. Program. Lang. Syst.	1993	DBLP DOI BibTeX RDF	RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
37	Thomas M. Morgan, Lawrence A. Rowe	Analyzing Exotic Instructions for a Retargetable Code Generator.	SIGPLAN Symposium on Compiler Construction	1982	DBLP DOI BibTeX RDF
37	David I. August, Wen-mei W. Hwu, Scott A. Mahlke	A Framework for Balancing Control Flow and Predication.	MICRO	1997	DBLP DOI BibTeX RDF	conditional instructions, if-conversion, predicated instructions, program control flow, schedule time, scheduling decisions, compiler, parallel architecture, instruction-level parallelism, optimising compilers, predicated execution
35	Mike Fournigault, Pierre-Yvan Liardet, Yannick Teglia, Alain Trémeau, Frédérique Robert-Inacio	Reverse Engineering of Embedded Software Using Syntactic Pattern Recognition.	OTM Workshops (1)	2006	DBLP DOI BibTeX RDF	Chip Instructions, Pattern Recognition, Reverse Engineering, Power Analysis, Side Channel
35	Ben H. H. Juurlink, Asadollah Shahbahrami, Stamatis Vassiliadis	Avoiding data conversions in embedded media processors.	SAC	2005	DBLP DOI BibTeX RDF	multimedia applications, SIMD instructions
35	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia	Micro embedded monitoring for security in application specific instruction-set processors.	CASES	2005	DBLP DOI BibTeX RDF	micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
35	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative Dynamic Vectorization.	ISCA	2002	DBLP DOI BibTeX RDF	Speculative dynamic vectorization, wide buses, speculative data computation, control independence, vector instructions
34	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	DIA: A Complexity-Effective Decoding Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
34	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Instruction set synthesis with efficient instruction encoding for configurable processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
34	Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary	Transparent control independence (TCI).	ISCA	2007	DBLP DOI BibTeX RDF	control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation
34	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
34	Jian Huang, David J. Lilja	Balancing Reuse Opportunities and Performance Gains with Subblock Value Reuse.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Block reuse, subblock reuse, compiler flow analysis, value reuse, value locality
34	Enric Musoll	Speculating to reduce unnecessary power consumption.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	low-power microarchitectures, Low-power design
34	Miroslav N. Velev	Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer.	DATE	2002	DBLP DOI BibTeX RDF
34	Vugranam C. Sreedhar, Roy Dz-Ching Ju, David M. Gillies, Vatsa Santhanam	Translating Out of Static Single Assignment Form.	SAS	1999	DBLP DOI BibTeX RDF
34	Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan	Speculation Techniques for Improving Load Related Instruction Scheduling.	ISCA	1999	DBLP DOI BibTeX RDF
34	Jay W. Warfield, Henry R. Bauer III	An expert system for a retargetable peephole optimizer.	ACM SIGPLAN Notices	1988	DBLP DOI BibTeX RDF
34	E. M. Boehm, Thomas B. Steel Jr.	The Share 709 System: Machine Implementation of Symbolic Programming.	J. ACM	1959	DBLP DOI BibTeX RDF
33	Seung-Won Na	Design and Implementation of Resource Sharing System for Creation of Multiple Instructions In Mobile Internet Environment.	WSTST	2005	DBLP DOI BibTeX RDF	Sharing of Mobile Resources, Ubiquitous Computing, Context-Awareness, multiple instructions
33	Antonio González 0001, José M. Llabería	Instruction fetch unit for parallel execution of branch instructions.	ICS	1989	DBLP DOI BibTeX RDF	instruction cache memory, zero time cost branches, pipelined processors, control dependencies, branch instructions
32	Thomas Gaudy, Stéphane Natkin, Dominique Archambault	Pyvox 2: An Audio Game Accessible to Visually Impaired People Playable without Visual Nor Verbal Instructions.	Trans. Edutainment	2009	DBLP DOI BibTeX RDF	interactivity, accessibility, usability test, sound design, interactive music, audio games
32	Asadollah Shahbahrami, Ben H. H. Juurlink	Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices.	APPT	2009	DBLP DOI BibTeX RDF
32	Martino Sykora, Giovanni Agosta, Cristina Silvano	Dynamic configuration of application-specific implicit instructions for embedded pipelined processors.	SAC	2008	DBLP DOI BibTeX RDF	implicit issue, reconfiguration, pipelined architecture
32	Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis	A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size.	SAMOS	2007	DBLP DOI BibTeX RDF
32	Joerg C. Wolf, Guido Bugmann	Understanding Rules in Human-Robot Instructions.	RO-MAN	2007	DBLP DOI BibTeX RDF
32	Neng-Fa Zhou	A Register-Free Abstract Prolog Machine with Jumbo Instructions.	ICLP	2007	DBLP DOI BibTeX RDF
32	Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis	A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.	ARC	2007	DBLP DOI BibTeX RDF
32	Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia	16-bit Floating Point Instructions for Embedded Multimedia Applications.	CAMP	2005	DBLP DOI BibTeX RDF
32	Neil Johnson 0002, Alan Mycroft	Using Multiple Memory Access Instructions for Reducing Code Size.	CC	2004	DBLP DOI BibTeX RDF
32	Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh	Instruction Selection for Compilers that Target Architectures with Echo Instructions.	SCOPES	2004	DBLP DOI BibTeX RDF
32	Adrián Cristal, Oliverio J. Santana, Mateo Valero	Maintaining Thousands of In-flight Instructions.	Euro-Par	2004	DBLP DOI BibTeX RDF
32	Pan Yu, Tulika Mitra	Scalable custom instructions identification for instruction-set extensible processors.	CASES	2004	DBLP DOI BibTeX RDF	subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
32	Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh	Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches.	DSD	2002	DBLP DOI BibTeX RDF
32	Martin Raubal, Stephan Winter 0001	Enriching Wayfinding Instructions with Local Landmarks.	GIScience	2002	DBLP DOI BibTeX RDF
32	Zhijie Shi, Ruby B. Lee	Subword Sorting with Versatile Permutation Instructions.	ICCD	2002	DBLP DOI BibTeX RDF
32	Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
32	Stamatis Vassiliadis, Ben H. H. Juurlink, Edwin A. Hakkennes	Complex Streamed Instructions: Introduction and Initial Evaluatio.	EUROMICRO	2000	DBLP DOI BibTeX RDF
32	Craig B. Zilles, Gurindar S. Sohi	Understanding the backward slices of performance degrading instructions.	ISCA	2000	DBLP DOI BibTeX RDF
32	Francesco Quaglia	Fast-Software-Checkpointing in Optimistic Simulation: Embedding State Saving into the Event Routine Instructions.	Workshop on Parallel and Distributed Simulation	1999	DBLP DOI BibTeX RDF
32	Allen Leung, Krishna V. Palem, Amir Pnueli	A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
32	Edward L. Robertson	Code Generation and Storage Allocation for Machines with Span-Dependent Instructions.	ACM Trans. Program. Lang. Syst.	1979	DBLP DOI BibTeX RDF
32	Amir M. Ben-Amram, Zvi Galil	When can we sort in o(n log n) time?	FOCS	1993	DBLP DOI BibTeX RDF	Boolean instructions, arithmetic instructions, nonuniform programs, double-precision multiplication, lower bounds, upper bounds, random access machine