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Publication years (Num. hits)
1956-1963 (19) 1964-1968 (15) 1969-1974 (16) 1975-1978 (20) 1979-1981 (19) 1982-1984 (23) 1985-1987 (47) 1988 (35) 1989 (32) 1990 (46) 1991 (16) 1992 (36) 1993 (34) 1994 (48) 1995 (56) 1996 (71) 1997 (92) 1998 (82) 1999 (158) 2000 (181) 2001 (150) 2002 (223) 2003 (309) 2004 (334) 2005 (380) 2006 (410) 2007 (374) 2008 (347) 2009 (246) 2010 (87) 2011 (47) 2012 (54) 2013 (53) 2014 (56) 2015 (44) 2016 (70) 2017 (76) 2018 (110) 2019 (111) 2020 (118) 2021 (113) 2022 (138) 2023 (209) 2024 (53)
Publication types (Num. hits)
article(1234) data(1) incollection(7) inproceedings(3889) phdthesis(27)
Venues (Conferences, Journals, ...)
CoRR(291) MICRO(137) ISCA(128) IEEE Trans. Computers(75) DATE(70) HPCA(66) IPDPS(63) ICS(62) ASPLOS(59) IEEE PACT(58) ICCD(53) PLDI(53) Euro-Par(52) CASES(46) CGO(43) ASAP(42) More (+10 of total 1372)
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The graphs summarize 4224 occurrences of 1958 keywords

Results
Found 5158 publication records. Showing 5158 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
92A. F. R. Brown Language Translation. Search on Bibsonomy J. ACM The full citation details ... 1958 DBLP  DOI  BibTeX  RDF
78Julie Heiser, Doantam Phan, Maneesh Agrawala, Barbara Tversky, Pat Hanrahan Identification and validation of cognitive design principles for automated generation of assembly instructions. Search on Bibsonomy AVI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF assembly instructions, visual instructions, diagrams, design principles, spatial ability
78A. P. Wim Böhm, John R. Gurd Iterative Instructions in the Manchester Dataflow Computer. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration
77Shay Gueron Intel's New AES Instructions for Enhanced Performance and Security. Search on Bibsonomy FSE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF new instructions set, computer architecture, Advanced Encryption Standard
77Sumeet Kumar, Aneesh Aggarwal Self-checking instructions: reducing instruction redundancy for concurrent error detection. Search on Bibsonomy PACT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures
74Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa Pack instruction generation for media pUsing multi-valued decision diagram. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-valued decision diagram, SIMD instructions
67Daniel Spelmezan, Mareike Jacobs, Anke Hilgers, Jan O. Borchers Tactile motion instructions for physical activities. Search on Bibsonomy CHI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF real-time instructions, sports training, vibrotactile feedack, physical activities, motor skills
63Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder Reducing code size with echo instructions. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF code size optimization, echo instructions, compression
61Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. Search on Bibsonomy CASES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sub-word parallelism, similarity measurements, SIMD
58Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. Search on Bibsonomy ASPLOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
57Sangho Ha, Sangyong Han, Heunghwan Kim Partitioning a lenient parallel language into sequential threads. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF lenient parallel language, language partitioning, sequential threads, multithreaded architecture performance, large-scale parallel system, split-phase memory operations, fast context switching, multithreaded code quality, enhanced thread formation scheme, Id/sup -/, long latency instructions, multiple switches, generalized switch-and-merge, thread merging, redundant arc elimination, thread precedence relations, control instructions, DAVRID multithreaded architecture, simulation, graph theory, parallel architectures, graph partitioning, switching, merging, parallel languages, large-scale systems, program control structures, branch instructions
56Jared Stark, Paul Racunas, Yale N. Patt Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF instruction supply, superscalar processors, out-of-order execution
55Sung-Kwan Kim, Sang Lyul Min, Rhan Ha Efficient worst case timing analysis of data caching. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
54Chia-Lin Yang, Barton Sano, Alvin R. Lebeck Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
53Enric Morancho, José María Llabería, Àngel Olivé Recovery Mechanism for Latency Misprediction. Search on Bibsonomy IEEE PACT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
53Arvind Krishnaswamy, Rajiv Gupta 0001 Enhancing the performance of 16-bit code using augmenting instructions. Search on Bibsonomy LCTES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF 16-bit thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, embedded processor, code size
52Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. Search on Bibsonomy MICRO The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Jingren Zhou, Kenneth A. Ross Implementing database operations using SIMD instructions. Search on Bibsonomy SIGMOD Conference The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
52David Hovemeyer, William W. Pugh, Jaime Spacco Atomic Instructions in Java. Search on Bibsonomy ECOOP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
52Hideo Wada, K. Ishil, Masakazu Fukagawa, H. Murayama, Shun Kawabe High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system. Search on Bibsonomy ICS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
49Hui Wang, Rama Sangireddy, Sandeep Baldawa Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
49J. Adam Butts, Gurindar S. Sohi Dynamic dead-instruction detection and elimination. Search on Bibsonomy ASPLOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
48Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, Toshio Nakatani A new idiom recognition framework for exploiting hardware-assist instructions. Search on Bibsonomy ASPLOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF VMX, hardware-assist instructions, idiom recognition, topological embedding, java, JIT
48Maneesh Agrawala, Doantam Phan, Julie Heiser, John Haymaker, Jeff Klingner, Pat Hanrahan, Barbara Tversky Designing effective step-by-step assembly instructions. Search on Bibsonomy ACM Trans. Graph. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF assembly instructions, visualization
47Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
44Vincent J. DiGri, Jane E. King The Share 709 System: Input-Output Translation. Search on Bibsonomy J. ACM The full citation details ... 1959 DBLP  DOI  BibTeX  RDF
42Aamer Jaleel, Bruce L. Jacob Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. Search on Bibsonomy HPCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Newton Cheung, Sri Parameswaran, Jörg Henkel A quantitative study and estimation models for extensible instructions in embedded processors. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai A Code Selection Method for SIMD Processors with PACK Instructions. Search on Bibsonomy SCOPES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
42Ruby B. Lee, A. Murat Fiskiran, Abdulla Bubsha Multimedia Instructions In IA-64. Search on Bibsonomy ICME The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
42Norman Ramsey, Mary F. Fernandez Specifying Representations of Machine Instructions. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF encoding, decoding, compiler generation, relocation, object code, machine description, machine code
42Norman Ramsey Relocating Machine Instructions by Currying. Search on Bibsonomy PLDI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
42John G. Cleary, Murray Pearson, Husam Kinawi The architecture of an optimistic CPU: the WarpEngine. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
39Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería On reducing misspeculations in a pipelined scheduler. Search on Bibsonomy IPDPS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Rama Sangireddy, Jatan P. Shah Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Andrew D. Hilton, Amir Roth Ginger: control independence using tag rewriting. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF control independence, out-of-order renaming, selective re-dispatch, branch misprediction
39Aamer Jaleel, Bruce L. Jacob In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
39Alexei Kudriavtsev, Peter M. Kogge Generation of permutations for SIMD processors. Search on Bibsonomy LCTES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SIMD, permutations
39Ching-Wen Chen, Chang-Jung Ku, Chih-Hung Chang Designing a High Performance and Low Energy-Consuming Embedded System with Considering Code Compressed Environments. Search on Bibsonomy RTCSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF decompression engine, performance, Embedded system, locality, power consumption, code compress
39Aamer Jaleel, Bruce L. Jacob Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. Search on Bibsonomy HiPC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Jack W. Davidson, David B. Whalley Ease: An Environment for Architecture Study and Experimentation. Search on Bibsonomy SIGMETRICS The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
38Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions. Search on Bibsonomy CGO The full citation details ... 2010 DBLP  DOI  BibTeX  RDF ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection
38Roan Boer Rookhuiszen, Mariët Theune Generating Instructions in a 3D Game Environment: Efficiency or Entertainment?. Search on Bibsonomy INTETAIN The full citation details ... 2009 DBLP  DOI  BibTeX  RDF efficiency vs. entertainment, evaluation, game, instructions, Natural Language Generation, 3D environment
38Daniel Spelmezan, Anke Hilgers, Jan O. Borchers A language of tactile motion instructions. Search on Bibsonomy Mobile HCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF motor skill learning, real-time instructions, sports training, tactile language, physical activities, vibrotactile feedback
38Luca Chittaro, Daniele Nadalutti Presenting evacuation instructions on mobile devices by means of location-aware 3D virtual environments. Search on Bibsonomy Mobile HCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF navigation instructions, mobile devices, RFID, 3D models, emergencies
38Atsuko K. Yamazaki, Joji Yabutani, Yoko Ebisawa, Satoshi Hori A Study of Meaning Comprehensibility of Pictograms for Lathe Procedural Instructions. Search on Bibsonomy KES (3) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF manufacturing instructions, communication, comprehensibility, pictogram
38Xuemeng Zhang, Rongcai Zhao, Jianmin Pang Semantic Abstraction of IA-64 Multimedia Instructions. Search on Bibsonomy SKG The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multimedia instructions, semantic abstraction, binary translation, IA-64
38Arvind Krishnaswamy, Rajiv Gupta 0001 Dynamic coalescing for 16-bit instructions. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF 16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size
38Philip Brisk, Jamie Macbeth 0001, Ani Nahapetian, Majid Sarrafzadeh A dictionary construction technique for code compression systems with echo instructions. Search on Bibsonomy LCTES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF (dictionary) compression, echo instructions, scheduling
38Zhijie Shi, Ruby B. Lee Bit Permutation Instructions for Accelerating Software Cryptography. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture
37Yedidya Hilewitz, Ruby B. Lee Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations
37Yuto Kawahara, Kazumaro Aoki, Tsuyoshi Takagi Faster Implementation of eta-T Pairing over GF(3m) Using Minimum Number of Logical Instructions for GF(3)-Addition. Search on Bibsonomy Pairing The full citation details ... 2008 DBLP  DOI  BibTeX  RDF GF(3)-addition, logical instruction, ? T pairing
37Kai-Florian Richter, Matt Duckham Simplest Instructions: Finding Easy-to-Describe Routes for Navigation. Search on Bibsonomy GIScience The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Pan Yu, Tulika Mitra Disjoint Pattern Enumeration for Custom Instructions Identification. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Enric Morancho, José María Llabería, Àngel Olivé On reducing energy-consumption by late-inserting instructions into the issue queue. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF L2 hit-miss prediction, memory-latency tolerant processors, energy consumption
37Yedidya Hilewitz, Ruby B. Lee Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. Search on Bibsonomy ASAP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Sung Dae Kim, Jung Hoo Lee, J. M. Yang, Myung Hoon Sunwoo, Seung Keun Oh Novel instructions and their hardware architecture for video signal processing. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Jinson Koppanalil, Eric Rotenberg A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture
37Krishna V. Palem, Barbara B. Simons Scheduling Time-Critical Instructions on RISC Machines. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
37Thomas M. Morgan, Lawrence A. Rowe Analyzing Exotic Instructions for a Retargetable Code Generator. Search on Bibsonomy SIGPLAN Symposium on Compiler Construction The full citation details ... 1982 DBLP  DOI  BibTeX  RDF
37David I. August, Wen-mei W. Hwu, Scott A. Mahlke A Framework for Balancing Control Flow and Predication. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF conditional instructions, if-conversion, predicated instructions, program control flow, schedule time, scheduling decisions, compiler, parallel architecture, instruction-level parallelism, optimising compilers, predicated execution
35Mike Fournigault, Pierre-Yvan Liardet, Yannick Teglia, Alain Trémeau, Frédérique Robert-Inacio Reverse Engineering of Embedded Software Using Syntactic Pattern Recognition. Search on Bibsonomy OTM Workshops (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Chip Instructions, Pattern Recognition, Reverse Engineering, Power Analysis, Side Channel
35Ben H. H. Juurlink, Asadollah Shahbahrami, Stamatis Vassiliadis Avoiding data conversions in embedded media processors. Search on Bibsonomy SAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multimedia applications, SIMD instructions
35Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia Micro embedded monitoring for security in application specific instruction-set processors. Search on Bibsonomy CASES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
35Alex Pajuelo, Antonio González 0001, Mateo Valero Speculative Dynamic Vectorization. Search on Bibsonomy ISCA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Speculative dynamic vectorization, wide buses, speculative data computation, control independence, vector instructions
34Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero DIA: A Complexity-Effective Decoding Architecture. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt Instruction set synthesis with efficient instruction encoding for configurable processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
34Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary Transparent control independence (TCI). Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation
34Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi Instruction-level test methodology for CPU core self-testing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
34Jian Huang, David J. Lilja Balancing Reuse Opportunities and Performance Gains with Subblock Value Reuse. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Block reuse, subblock reuse, compiler flow analysis, value reuse, value locality
34Enric Musoll Speculating to reduce unnecessary power consumption. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power microarchitectures, Low-power design
34Miroslav N. Velev Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Vugranam C. Sreedhar, Roy Dz-Ching Ju, David M. Gillies, Vatsa Santhanam Translating Out of Static Single Assignment Form. Search on Bibsonomy SAS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan Speculation Techniques for Improving Load Related Instruction Scheduling. Search on Bibsonomy ISCA The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Jay W. Warfield, Henry R. Bauer III An expert system for a retargetable peephole optimizer. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
34E. M. Boehm, Thomas B. Steel Jr. The Share 709 System: Machine Implementation of Symbolic Programming. Search on Bibsonomy J. ACM The full citation details ... 1959 DBLP  DOI  BibTeX  RDF
33Seung-Won Na Design and Implementation of Resource Sharing System for Creation of Multiple Instructions In Mobile Internet Environment. Search on Bibsonomy WSTST The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Sharing of Mobile Resources, Ubiquitous Computing, Context-Awareness, multiple instructions
33Antonio González 0001, José M. Llabería Instruction fetch unit for parallel execution of branch instructions. Search on Bibsonomy ICS The full citation details ... 1989 DBLP  DOI  BibTeX  RDF instruction cache memory, zero time cost branches, pipelined processors, control dependencies, branch instructions
32Thomas Gaudy, Stéphane Natkin, Dominique Archambault Pyvox 2: An Audio Game Accessible to Visually Impaired People Playable without Visual Nor Verbal Instructions. Search on Bibsonomy Trans. Edutainment The full citation details ... 2009 DBLP  DOI  BibTeX  RDF interactivity, accessibility, usability test, sound design, interactive music, audio games
32Asadollah Shahbahrami, Ben H. H. Juurlink Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Martino Sykora, Giovanni Agosta, Cristina Silvano Dynamic configuration of application-specific implicit instructions for embedded pipelined processors. Search on Bibsonomy SAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF implicit issue, reconfiguration, pipelined architecture
32Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Joerg C. Wolf, Guido Bugmann Understanding Rules in Human-Robot Instructions. Search on Bibsonomy RO-MAN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Neng-Fa Zhou A Register-Free Abstract Prolog Machine with Jumbo Instructions. Search on Bibsonomy ICLP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. Search on Bibsonomy ARC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia 16-bit Floating Point Instructions for Embedded Multimedia Applications. Search on Bibsonomy CAMP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Neil Johnson 0002, Alan Mycroft Using Multiple Memory Access Instructions for Reducing Code Size. Search on Bibsonomy CC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh Instruction Selection for Compilers that Target Architectures with Echo Instructions. Search on Bibsonomy SCOPES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Adrián Cristal, Oliverio J. Santana, Mateo Valero Maintaining Thousands of In-flight Instructions. Search on Bibsonomy Euro-Par The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Pan Yu, Tulika Mitra Scalable custom instructions identification for instruction-set extensible processors. Search on Bibsonomy CASES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
32Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Martin Raubal, Stephan Winter 0001 Enriching Wayfinding Instructions with Local Landmarks. Search on Bibsonomy GIScience The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Zhijie Shi, Ruby B. Lee Subword Sorting with Versatile Permutation Instructions. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Stamatis Vassiliadis, Ben H. H. Juurlink, Edwin A. Hakkennes Complex Streamed Instructions: Introduction and Initial Evaluatio. Search on Bibsonomy EUROMICRO The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
32Craig B. Zilles, Gurindar S. Sohi Understanding the backward slices of performance degrading instructions. Search on Bibsonomy ISCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
32Francesco Quaglia Fast-Software-Checkpointing in Optimistic Simulation: Embedding State Saving into the Event Routine Instructions. Search on Bibsonomy Workshop on Parallel and Distributed Simulation The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Allen Leung, Krishna V. Palem, Amir Pnueli A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP. Search on Bibsonomy IEEE PACT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
32Edward L. Robertson Code Generation and Storage Allocation for Machines with Span-Dependent Instructions. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1979 DBLP  DOI  BibTeX  RDF
32Amir M. Ben-Amram, Zvi Galil When can we sort in o(n log n) time? Search on Bibsonomy FOCS The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Boolean instructions, arithmetic instructions, nonuniform programs, double-precision multiplication, lower bounds, upper bounds, random access machine
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