Search results for "Layouts"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Sung-Eui Yoon, Peter Lindstrom 0001	Mesh Layouts for Block-Based Caches.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	Mesh and graph layouts, cache-aware and cache-oblivious layouts, metrics for cache coherence, data locality
81	Leszek Gasieniec, Evangelos Kranakis, Danny Krizanc, Andrzej Pelc	Minimizing Congestion of Layouts for ATM Networks with Faulty Links.	MFCS	1996	DBLP DOI BibTeX RDF
81	Eric J. Schwabe, Ian M. Sutherland	Improved Parity-Declustered Layouts for Disk Arrays.	SPAA	1994	DBLP DOI BibTeX RDF
74	Andreas Noack, Claus Lewerentz	A space of layout styles for hierarchical graph models of software systems.	SOFTVIS	2005	DBLP DOI BibTeX RDF	force-directed methods, clustering, information visualization, reverse engineering, refactoring, program understanding, software visualization, graph drawing, focus + context
73	Tim Dwyer, Bongshin Lee, Danyel Fisher, Kori Inkpen Quinn, Petra Isenberg, George G. Robertson, Chris North 0001	A Comparison of User-Generated and Automatic Graph Layouts.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
73	Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K. Patnala, Mithuna Thottethodi	Recursive Array Layouts and Fast Matrix Multiplication.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	matrix multiplication, Data layout
70	Adam L. Buchsbaum, Emden R. Gansner, Cecilia Magdalena Procopiuc, Suresh Venkatasubramanian	Rectangular layouts and contact graphs.	ACM Trans. Algorithms	2008	DBLP DOI BibTeX RDF	Contact graphs, rectangular duals, rectangular layouts
59	Aidan Slingsby, Jason Dykes, Jo Wood	Configuring Hierarchical Layouts to Address Research Questions.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
59	Martin Hirzel	Data layouts for object-oriented programs.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	GC, cache, data placement, spatial locality, data layout, TLB, hardware performance counters, memory subsystem
55	Luis Francisco-Revilla, Jeff Crow	Interpretation of web page layouts by blind users.	JCDL	2010	DBLP DOI BibTeX RDF	web page layouts, assistive technology, blind users
52	Angelo Di Iorio, Luca Furini, Fabio Vitali, John William Lumley, Tony Wiley	Higher-level layout through topological abstraction.	ACM Symposium on Document Engineering	2008	DBLP DOI BibTeX RDF	DDF, TALL, topological layouts, XSLT, automatic layouts
52	Guillermo A. Alvarez, Walter A. Burkhard, Larry J. Stockmeyer, Flaviu Cristian	Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism.	ISCA	1998	DBLP DOI BibTeX RDF
51	Won-Taek Lim, Mithuna Thottethodi	Evaluating ISA Support and Hardware Support for Recursive Data Layouts.	HiPC	2007	DBLP DOI BibTeX RDF
51	Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee	A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
51	King C. Ho, Sarma B. K. Vrudhula	Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
48	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee	A Layout-Conscious Iteration Space Transformation Technique.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	program optimization, loop transformations, Data reuse, cache locality, memory layouts
44	Bonita Sharif, Jonathan I. Maletic	An empirical study on the comprehension of stereotyped UML class diagram layouts.	ICPC	2009	DBLP DOI BibTeX RDF
44	Marius Nita, Dan Grossman	Automatic Transformation of Bit-Level C Code to Support Multiple Equivalent Data Layouts.	CC	2008	DBLP DOI BibTeX RDF
44	Michele Flammini, Enrico Nardelli, Guido Proietti	ATM layouts with bounded hop count and congestion.	Distributed Comput.	2001	DBLP DOI BibTeX RDF	Edge and node congestion, Routing, Computational complexity, ATM networks
44	Mahmut T. Kandemir, Ismail Kadayif	Compiler-directed selection of dynamic memory layouts.	CODES	2001	DBLP DOI BibTeX RDF	array reuse, memory layout optimization, software compilation, data dependence, data locality
44	Mahmut T. Kandemir, Alok N. Choudhary, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam	A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	array restructuring, parallelism, Data reuse, spatial locality, memory performance, locality optimizations
44	Michele Flammini, Enrico Nardelli, Guido Proietti	ATM Layouts with Bounded Hop Count and Congestion.	WDAG	1997	DBLP DOI BibTeX RDF
44	Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner 0001, Karsten Weihe	Wiring Knock-Knee Layouts: A Global Appoach.	ISAAC	1992	DBLP DOI BibTeX RDF
41	Luis Francisco-Revilla, Jeff Crow	Interpreting the layout of web pages.	Hypertext	2009	DBLP DOI BibTeX RDF	modular layouts, sighted users, assistive technology, adaptive hypermedia, visually impaired users, spatial hypermedia
41	Sung-Eui Yoon, Peter Lindstrom 0001	Random-Accessible Compressed Triangle Meshes.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	cache-coherent layouts, mesh data structures, random access, external memory algorithms, Mesh compression
41	Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé	Static and Dynamic Locality Optimizations Using Integer Linear Programming.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	cache miss estimation, compiler optimizations, integer linear programming, Data reuse, cache locality, memory layouts
41	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
38	Romas Aleliunas, Arnold L. Rosenberg	On Embedding Rectangular Grids in Square Grids.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	theory of VLSI layouts, Bounding aspect ratios of layouts, embedding graphs in grids, graph embeddings, generic graphs
37	Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati	Evaluation of Offset Assignment Heuristics.	HiPEAC	2007	DBLP DOI BibTeX RDF
37	Jae-Gon Kim, Marc Goetschalckx	A Mixed Integer Programming Model for Modifying a Block Layout to Facilitate Smooth Material Flows.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
37	Qinglang Luo, Xianlong Hong, Qiang Zhou 0001, Yici Cai	A new algorithm for layout of dark field alternating phase shifting masks.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	AltPSM, space division strategy, VLSI
37	Ismail Kadayif, Mahmut T. Kandemir	Quasidynamic Layout Optimizations for Improving Data Locality.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	array-intensive computations, dynamic optimization, Optimizing compilers, data locality
37	Hiroshi Hosobe	A high-dimensional approach to interactive graph visualization.	SAC	2004	DBLP DOI BibTeX RDF	general undirected graphs, interactive graph layout, information visualization, multidimensional scaling
37	Chi-Hsiang Yeh	Optimal Layout for Butterfly Networks in Multilayer VLSI.	ICPP	2003	DBLP DOI BibTeX RDF
37	Yannis E. Ioannidis, Miron Livny, Jian Bao, Eben M. Haber	User-oriented visual layout at multiple granularities.	AVI	1996	DBLP DOI BibTeX RDF
36	Krystian Samp, Stefan Decker	Supporting menu design with radial layouts.	AVI	2010	DBLP DOI BibTeX RDF	radial layout, menus
36	Khaled Jouini, Geneviève Jomier, Patrick Kabore	Read-Optimized, Cache-Conscious, Page Layouts for Temporal Relational Data.	DEXA	2008	DBLP DOI BibTeX RDF
36	Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei	A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts.	VLSI Design	2008	DBLP DOI BibTeX RDF
36	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.	ISQED	2007	DBLP DOI BibTeX RDF
36	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Multilevel symmetry-constraint generation for retargeting large analog layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Xiaoping Tang, Xin Yuan	Technology migration techniques for simplified layouts with restrictive design rules.	ICCAD	2006	DBLP DOI BibTeX RDF
36	Anand Pramod Kulkarni, Thomas J. Grebinski	mTest: An Industry-Wide Database of VLSI Layouts for Quality Control.	ISQED	2006	DBLP DOI BibTeX RDF
36	Sung-Eui Yoon, Peter Lindstrom 0001, Valerio Pascucci, Dinesh Manocha	Cache-oblivious mesh layouts.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF
36	Jayaprakash Pisharath, Wei-keng Liao, Alok N. Choudhary	Design and Evaluation of Database Layouts for MEMS-Based Storage Systems.	IDEAS	2005	DBLP DOI BibTeX RDF
36	Jack Kustanowitz, Ben Shneiderman	Meaningful presentations of photo libraries: rationale and applications of bi-level radial quantum layouts.	JCDL	2005	DBLP DOI BibTeX RDF	layout generation, photo management, visual presentation, user interfaces, digital libraries
36	Evangelia Athanasaki, Nectarios Koziris	Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache Locality.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
36	David Peleg, Uri Pincas	The Average Hop Count Measure for Virtual Path Layouts.	DISC	2001	DBLP DOI BibTeX RDF
36	Tak-Kwong Ng, S. Lennart Johnsson	Generation of layouts from MOS circuit schematics: a graph theoretic approach.	DAC	1985	DBLP DOI BibTeX RDF
34	Yokesh Kumar, Prosenjit Gupta	External memory layout vs. schematic.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	verification of layouts, Graph, design automation, external memory algorithms, subgraph isomorphism
34	Yi Liu, Hongbin Zha, Hong Qin 0001	The Generalized Shape Distributions for Shape Matching and Analysis.	SMI	2006	DBLP DOI BibTeX RDF	Shape distributions, Vector quantization and spatial layouts, Spin images
34	Mahmut T. Kandemir	A compiler technique for improving whole-program locality.	POPL	2001	DBLP DOI BibTeX RDF	static optimizations, optimizing compilers, data reuse, cache locality, memory layouts
34	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.	DATE	1998	DBLP DOI BibTeX RDF	Gallium Arsenide automated layout generation system, GaAs VLSI design, power supply and ground distribution model, full-custom cell layout style, full-custom layouts of very high speed circuits, cell library builder, random logic macrocell generator, iterative logic array generator
33	David Eppstein, Elena Mumford, Bettina Speckmann, Kevin Verbeek	Area-universal rectangular layouts.	SCG	2009	DBLP DOI BibTeX RDF	rectangular layouts
33	Ruixuan Wang, Stephen J. McKenna, Junwei Han	High-entropy layouts for content-based browsing and retrieval.	CIVR	2009	DBLP DOI BibTeX RDF	content-based browsing and retrieval, image layouts, manifold learning, Renyi entropy
33	Sunyu Hwang, Geehyuk Lee	Qwerty-like 3x4 keypad layouts for mobile phone.	CHI Extended Abstracts	2005	DBLP DOI BibTeX RDF	QWERTY keyboard layout, QWERTY-like keypad layouts, mobile phone
33	Takeo Igarashi, Satoshi Matsuoka, Toshiyuki Masui	Adaptive Recognition of Implicit Structures in Human-Organized Layouts.	VL	1995	DBLP DOI BibTeX RDF	idea processors, human-organized layouts, card handling, hypertext editor, complex problem understanding, ambiguous structures, user-specific perception, rule-based spatial parsing algorithm, spatial parser, adaptive customization, interactive suggestion process, genetic algorithms, genetic algorithm, pattern recognition, graphical user interfaces, human factors, hypermedia, visual languages, adaptive systems, interactive systems, grammars, user preferences, human perception, uncertainty handling, ideas generation, implicit structures, adaptive recognition
30	Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala	Efficient Analog/RF Layout Closure with Compaction Based Legalization.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Daniel G. Aliaga, Carlos A. Vanegas, Bedrich Benes	Interactive example-based urban layout synthesis.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	content-aware image editing, texture and image synthesis, procedural modeling, example-based
30	Chengliang Zhang, Martin Hirzel	Online Phase-Adaptive Data Layout Selection.	ECOOP	2008	DBLP DOI BibTeX RDF
30	Andre Suslik Spritzer, Carla Maria Dal Sasso Freitas	A physics-based approach for interactive manipulation of graph visualizations.	AVI	2008	DBLP DOI BibTeX RDF	interaction, graph visualization
30	Oliver Pell	Verification of FPGA Layout Generators in Higher-Order Logic.	J. Autom. Reason.	2006	DBLP DOI BibTeX RDF	layout description, circuit verification, FPGA, theorem proving
30	Unmil Karadkar, Marlo Nordt, Richard Furuta, Cody Lee, Christopher M. Quick	An Exploration of Space-Time Constraints on Contextual Information in Image-Based Testing Interfaces.	ECDL	2006	DBLP DOI BibTeX RDF
30	Damian Merrick, Joachim Gudmundsson	Increasing the readability of graph drawings with centrality-based scaling.	APVIS	2006	DBLP DOI BibTeX RDF	metro maps, graph drawing, centrality
30	Jérôme Simonin, Suzanne Kieffer, Noëlle Carbonell	Influence de l'organisation spatiale des affichages sur l'efficacité de la recherche visuelle.	IHM	2005	DBLP DOI BibTeX RDF	eye-tracking analysis, gaze study, software ergonomics, spatial layout of displays, human-computer interaction, visual search
30	Jérôme Simonin, Suzanne Kieffer, Noelle Carbonell	Effects of Display Layout on Gaze Activity During Visual Search.	INTERACT	2005	DBLP DOI BibTeX RDF
30	Hung-Ming Sun	Page Segmentation for Manhattan and Non-Manhattan Layout Documents via Selective CRLA.	ICDAR	2005	DBLP DOI BibTeX RDF
30	Baback Moghaddam, Qi Tian 0001, Neal Lesh, Chia Shen, Thomas S. Huang	Visualization and User-Modeling for Browsing Personal Photo Libraries.	Int. J. Comput. Vis.	2004	DBLP DOI BibTeX RDF	visualization, PCA, estimation, CBIR, subspace analysis
30	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.	ASP-DAC	2004	DBLP DOI BibTeX RDF
30	Sujit T. Zachariah, Sreejit Chakravarty	A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz Parhami	Multilayer VLSI Layout for Interconnection Networks.	ICPP	2000	DBLP DOI BibTeX RDF
30	Jeffrey P. Bradford, Russell W. Quong	An empirical study on how program layout affects cache miss rates.	SIGMETRICS Perform. Evaluation Rev.	1999	DBLP DOI BibTeX RDF
30	Ken Kennedy, Ulrich Kremer	Automatic Data Layout for Distributed-Memory Machines.	ACM Trans. Program. Lang. Syst.	1998	DBLP DOI BibTeX RDF	high performance Fortran
29	Holger Gast	Reasoning about Memory Layouts.	FM	2009	DBLP DOI BibTeX RDF
29	Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy	Cell Swapping Based Migration Methodology for Analog and Custom Layouts.	ISQED	2008	DBLP DOI BibTeX RDF	Layout migration, compaction, constraint generation
29	Lihong Zhang, Ulrich Kleine, Yingtao Jiang	An automated design tool for analog layouts.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
29	Emden R. Gansner, Yehuda Koren	Improved Circular Layouts.	GD	2006	DBLP DOI BibTeX RDF
29	Arnaud Puret, Sebastien Aupetit, Pierre Gaucher, Nicolas Monmarché, Mohamed Slimane	Selection by Visualization of Topological Layouts for Adapted Living Area Design.	ICCHP	2006	DBLP DOI BibTeX RDF
29	Michele Flammini, Giorgio Gambosi, Alfredo Navarra	Wireless ATM Layouts for Chain Networks.	Mob. Networks Appl.	2005	DBLP DOI BibTeX RDF	wireless networks, ATM networks, capacity planning, mobile users, chains
29	Ibrahim Cahit, Ahmet Adalier	New Layouts for Multi-stage Interconnection Networks.	ICN (1)	2005	DBLP DOI BibTeX RDF
29	Manish Garg, Aatish Kumar, Johannes van Wingerden, Laurent Le Cam	Litho-driven layouts for reducing performance variability.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
29	Evangelia Athanasaki, Kornilios Kourtis, Nikos Anastopoulos, Nectarios Koziris	Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
29	Evangelia Athanasaki, Nectarios Koziris	Improving Cache Locality with Blocked Array Layouts.	PDP	2004	DBLP DOI BibTeX RDF
29	Vincent W. L. Tam, Simon Koo, Kozo Sugiyama	Evolving Artificial Ant Systems to Improve Layouts of Graphical Objects.	PRICAI	2004	DBLP DOI BibTeX RDF
29	Michael Baur, Ulrik Brandes	Crossing Reduction in Circular Layouts.	WG	2004	DBLP DOI BibTeX RDF
29	Michele Flammini, Giorgio Gambosi, Alfredo Navarra	Wireless ATM Layouts for Chain Networks.	IPDPS	2003	DBLP DOI BibTeX RDF	wireless networks, ATM networks, mobile users, chains
29	Angelo Brambilla, Paolo Maffezzoni	Statistical method for the analysis of interconnects delay insubmicrometer layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
29	Shmuel Zaks	On the Use of Duality and Geometry in Layouts for ATM Networks.	MFCS	2000	DBLP DOI BibTeX RDF
29	Massoud Pedram, Bryan Preas	Interconnection analysis for standard cell layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	Markus Wolf 0001, Ulrich Kleine	Reliability driven module generation for analog layouts.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
29	Emden R. Gansner, Stephen C. North	Improved Force-Directed Layouts.	GD	1998	DBLP DOI BibTeX RDF
29	Dinesh P. Mehta, George Blust	Corner stitching for simple rectilinear shapes [VLSI layouts].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
29	Scott E. Hudson, Chen-Ning Hsi	A synergistic approach to specifying simple number independent layouts by example.	INTERCHI	1993	DBLP DOI BibTeX RDF	end-user customization, grid-based layout, layout specification, generalization, programming by example
29	Ioannis G. Tollis	A new approach to wiring layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
29	Deepak D. Sherlekar	Optimality of Gauge and Degree-Sensitive VLSI Layouts of Planar Graphs.	ICCI	1990	DBLP DOI BibTeX RDF
29	Musaravakkam S. Krishnan, John P. Hayes	A normalized-area measure for VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
29	Bernd Becker 0001, Hans-Georg Osthof	Layouts with Wires of Balanced Length.	STACS	1985	DBLP DOI BibTeX RDF
26	Takuto Yanagida, Hidetoshi Nonaka, Masahito Kurihara	Personalizing graphical user interfaces on flexible widget layout.	EICS	2009	DBLP DOI BibTeX RDF	flexible widget layouts, fuzzy constraint satisfaction problems, personalization of graphical user interfaces, optimization, adaptive user interfaces
26	Sung-Eui Yoon, Christian Lauterbach, Dinesh Manocha	R-LODs: fast LOD-based ray tracing of massive models.	Vis. Comput.	2006	DBLP DOI BibTeX RDF	Massive models, LODs, Ray tracing, Layouts, Cache coherence, kd-trees
26	Jun Xia, Li Luo, Xuejun Yang	A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	compiler optimizations, integer linear programming, loop transformations, data transformations, Cache locality, memory layouts
26	I-Lun Tseng, Adam Postula	An efficient algorithm for partitioning parameterized polygons into rectangles.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	corner stitching, parameterized layouts, parameterized polygons, polygon decomposition