Search results for "MPSOC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Yu Wang 0002, Jiang Xu 0001, Shengxi Huang, Weichen Liu, Huazhong Yang	A case study of on-chip sensor network in multiprocessor system-on-chip.	CASES	2009	DBLP DOI BibTeX RDF	sensor network, reliability, low-power, system on chip, dynamic control, power grid noise
95	Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick	Application-Specific MPSoC Reliability Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
83	Liping Xue, Ozcan Ozturk 0001, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu	Dynamic partitioning of processing and memory resources in embedded MPSoC architectures.	DATE	2006	DBLP DOI BibTeX RDF
73	David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias	A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.	DAC	2006	DBLP DOI BibTeX RDF	thermal studies, FPGA, emulation, MPSoC
72	Yuriy Sheynin, Elena Suvorova, Felix Shutenko	Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design.	ISVLSI	2006	DBLP DOI BibTeX RDF
66	Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A high-level virtual platform for early MPSoC software development.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	simulation, parallel programming, software, embedded, MPSoC, system level design, virtual platform
66	Eric Cheung, Harry Hsieh, Felice Balarin	Software optimization for MPSoC: a mpeg-2 decoder case study.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	mpsoc, software optimization
66	Hong Yue, Zhiying Wang 0003, Kui Dai	A Heterogeneous Embedded MPSoC for Multimedia Applications.	HPCC	2006	DBLP DOI BibTeX RDF	Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC
62	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
62	Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller	Multicore design is the challenge! what is the solution?	DAC	2008	DBLP DOI BibTeX RDF	heterogeneous/homogenous multicore, symmetric/asymmetric multicore, multiprocessors, interconnect, multi-core, MPSoC, programming model, virtual prototyping, ESL, virtual platforms
62	Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Multiprocessor performance estimation using hybrid simulation.	DAC	2008	DBLP DOI BibTeX RDF	HySim, address recovery, cross replay, MPSoC, performance estimation, cache simulation, hybrid simulation
62	David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida	HW-SW emulation framework for temperature-aware design in MPSoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Thermal-aware design, FPGA, emulation, MPSoC, temperature
62	Wayne H. Wolf	The future of multiprocessor systems-on-chips.	DAC	2004	DBLP DOI BibTeX RDF	real-time, low power, system-on-chip, embedded software, MPSoC
61	Eric Cheung, Harry Hsieh, Felice Balarin	Fast and accurate performance simulation of embedded software for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
55	Qiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit	Cognitive Radio Design on an MPSoC Reconfigurable Platform.	Mob. Networks Appl.	2008	DBLP DOI BibTeX RDF	task transaction level interface, sparse FFT, OFDM, cognitive radio, design method, MPSoC
55	Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda	MAPS: an integrated framework for MPSoC application parallelization.	DAC	2008	DBLP DOI BibTeX RDF	MPSoC programming, parallelization, software, embedded
55	Ines Viskic, Samar Abdi, Daniel D. Gajski	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.	LCTES	2007	DBLP DOI BibTeX RDF	custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
55	Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar	Adaptive Sampling for Efficient MPSoC Architecture Simulation.	MASCOTS	2007	DBLP DOI BibTeX RDF	Simulation, Sampling, MPSoC, Acceleration
55	Pramod Chandraiah, Rainer Dömer	Pointer re-coding for creating definitive MPSoC models.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	re-coding, MPSoC, pointers, system specification
55	Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra	Integrated scratchpad memory optimization and task scheduling for MPSoC architectures.	CASES	2006	DBLP DOI BibTeX RDF	scheduling, MPSoC, scratchpad memory, task mapping
55	Julien Bernard 0001, Jean-Louis Roch, Serge De Paoli, Miguel Santana	Adaptive Encoding of Multimedia Streams on MPSoC.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF	scheduling, MPSoC, work-stealing
55	Grant Martin	Overview of the MPSoC design challenge.	DAC	2006	DBLP DOI BibTeX RDF	MPSoC, system-level design, multi-processor system-on-chip
55	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin	Using data compression in an MPSoC architecture for improving performance.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	compression, MPSoC
51	Salvatore Carta, Andrea Acquaviva, Pablo García Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias	Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	thermal studies, FPGA, operating system, emulation, MPSoC
49	Francesco Zanini, David Atienza, Giovanni De Micheli	A control theory approach for thermal balancing of MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
49	Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung	A unified power measurement and management platform for pipelined MPSoC executions.	SoCC	2008	DBLP DOI BibTeX RDF
49	Sudeep Pasricha, Nikil D. Dutt	A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
49	Katalin Popovici, Ahmed Amine Jerraya	Simulink based hardware-software codesign flow for heterogeneous MPSoC.	SCSC	2007	DBLP BibTeX RDF	hardware-software gradual refinement, multimedia applications, abstraction levels
49	Youssef Atat, Nacer-Eddine Zergainoh	Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
49	Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor	System level assessment of an optical NoC in an MPSoC platform.	DATE	2007	DBLP DOI BibTeX RDF
49	Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser	An MPSoC Performance Estimation Framework Using Transaction Level Modeling.	RTCSA	2007	DBLP DOI BibTeX RDF
49	Andrea Marongiu, Luca Benini, Mahmut T. Kandemir	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.	CASES	2007	DBLP DOI BibTeX RDF	code parallelization, MPSoCs, barrier synchronization
49	Tianmiao Wang, Kai Sun, Hongxing Wei, Meng Wang 0005, Zili Shao, Hui Liu 0006	Interconnection Synthesis of MPSoC Architecture for Gamma Cameras.	EUC	2007	DBLP DOI BibTeX RDF
49	Pramod Chandraiah, Rainer Dömer	Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification.	DAC	2007	DBLP DOI BibTeX RDF
49	Sudeep Pasricha, Nikil D. Dutt	COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
49	Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund	PAM-SoC: A Toolchain for Predicting MPSoC Performance.	Euro-Par	2006	DBLP DOI BibTeX RDF
49	Terry Tao Ye, Luca Benini, Giovanni De Micheli	Packetized On-Chip Interconnect Communication Analysis for MPSoC.	DATE	2003	DBLP DOI BibTeX RDF
45	Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal	A tuneable software cache coherence protocol for heterogeneous MPSoCs.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	performance, design, reliability
45	Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir	Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
45	Roman Obermaisser, Hubert Kraut, Christian El Salloum	A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR.	EDCC	2008	DBLP DOI BibTeX RDF
45	Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli	A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
44	Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor	A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.	DAC	2010	DBLP DOI BibTeX RDF	embedded systems, MPSoC, memory optimization
44	Bjorn De Sutter, Diederik Verkest, Erik Brockmeyer, Eric Delfosse, Arnout Vandecappelle, Jean-Yves Mignolet	Design and Tool Flow of Multimedia MPSoC Platforms.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Tool flow, Multimedia, Parallelization, Predictability, MPSoC
44	Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot	Native MPSoC co-simulation environment for software performance estimation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	code annotation, MPSoC, system simulation, cross-compilation
44	Anders Sejer Tranberg-Hansen, Jan Madsen	A compositional modelling framework for exploring MPSoC systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	MPSoC, system level design, performance estimation
44	Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva	Cache coherency communication cost in a NoC-based MPSoC platform.	SBCCI	2007	DBLP DOI BibTeX RDF	cache coherence, MPSoC, NoC, directory
44	Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001, Mustafa Karaköy	Selective code/data migration for reducing communication energy in embedded MpSoC architectures.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	energy, migration, MPSoC
44	Slo-Li Chu	POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture.	ICPADS (2)	2005	DBLP DOI BibTeX RDF	POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
44	Feihui Li, Mahmut T. Kandemir	Locality-conscious workload assignment for array-based computations in MPSOC architectures.	DAC	2005	DBLP DOI BibTeX RDF	MPSoC, data locality
40	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
40	Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Anne-Marie Fouillart, Frédéric Pétrot, Ahmed Amine Jerraya	Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	HW/SW interfaces, Programming models, heterogeneous MPSoC
40	Grant Martin	Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	MPSoC, programming models, dataflow, instruction-set extension, multiprocessor system-on-chip, configurable processor, electronic system-level design
40	Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot	Programming models and HW-SW interfaces abstraction for multi-processor SoC.	DAC	2006	DBLP DOI BibTeX RDF	HW/SW interfaces, programming models, heterogeneous MPSoC
38	Ines Viskic, Lochi Yu, Daniel Gajski	Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications.	LCTES	2010	DBLP DOI BibTeX RDF	kahn process, transaction level model, automatic generation, process network, process mapping
38	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
38	Hao Shen, Frédéric Pétrot	Novel task migration framework on configurable heterogeneous MPSoC platforms.	ASP-DAC	2009	DBLP DOI BibTeX RDF
38	Katalin Popovici, Ahmed Amine Jerraya	Flexible and abstract communication and interconnect modeling for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
38	Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann	Fast model-based test case classification for performance analysis of multimedia MPSoC platforms.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	multimedia, workload, video classification
38	Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen	A Reactive and Cycle-True IP Emulator for MPSoC Exploration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
38	Wayne H. Wolf, Ahmed Amine Jerraya, Grant Martin	Multiprocessor System-on-Chip (MPSoC) Technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
38	Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek	A retargetable parallel-programming framework for MPSoC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	parallel-programming, design-space exploration, Embedded software, multiprocessor system on chip, software generation
38	Patrice Gerin, Xavier Guerin, Frédéric Pétrot	Efficient Implementation of Native Software Simulation for MPSoC.	DATE	2008	DBLP DOI BibTeX RDF
38	Bart D. Theelen	Performance Model Generation for MPSoC Design-Space Exploration.	QEST	2008	DBLP DOI BibTeX RDF
38	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.	DSD	2008	DBLP DOI BibTeX RDF
38	Luca Benini, Davide Bertozzi, Michela Milano	Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.	ICLP	2008	DBLP DOI BibTeX RDF
38	Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal	Intra- and inter-processor hybrid performance modeling for MPSoC architectures.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	simulation, performance analysis, system-on-chip
38	Anders Sejer Tranberg-Hansen, Jan Madsen, Bjørn Sand Jensen	A service based estimation method for MPSoC performance modelling.	SIES	2008	DBLP DOI BibTeX RDF
38	Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser	An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.	ASAP	2008	DBLP DOI BibTeX RDF
38	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
38	Vincent Nollet, Diederik Verkest, Henk Corporaal	A Quick Safari Through the MPSoC Run-Time Management Jungle.	ESTIMedia	2007	DBLP DOI BibTeX RDF
38	AbdelHalim Samahi, El-Bay Bourennane	Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform.	AHS	2007	DBLP DOI BibTeX RDF
38	Kai Huang 0002, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya	Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.	DAC	2007	DBLP DOI BibTeX RDF
38	Yuan Xie 0001, Wei-Lun Hung	Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	thermal-aware design, scheduling, embedded system design, system-on-chip design
38	Junggyu Park, Hyojung Song, Seungmo Cho, Najeong Han, Kyungjeon Kim, Jinman Park	A Real-time Media Framework for Asymmetric MPSoC.	ISORC	2006	DBLP DOI BibTeX RDF
38	Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya	Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
38	Wolfgang Klingauf, Hagen Gädke, Robert Günzel	TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
38	Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser	Estimating Energy Consumption for an MPSoC Architectural Exploration.	ARCS	2006	DBLP DOI BibTeX RDF
38	Peter Flake, Simon J. Davidmann, Frank Schirrmeister	System-level exploration tools for MPSoC designs.	DAC	2006	DBLP DOI BibTeX RDF	simulation, software development, debugging, multicore
38	Shankar Mahadevan, Michael Storgaard, Jan Madsen, Kashif Virk	ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality.	MASCOTS	2005	DBLP DOI BibTeX RDF
38	Ivan Petkov, Paul Amblard, Marin Hristov	Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoC.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
38	Ali Erdem Özcan, Sébastien Jean, Jean-Bernard Stefani	Bringing Ease and Adaptability to MPSoC Software Design: A Component-Based Approach.	CASSIS	2005	DBLP DOI BibTeX RDF
38	Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya	Debugging HW/SW interface for MPSoC: video encoder system design case study.	DAC	2004	DBLP DOI BibTeX RDF	hardware-dependant software, hardware-software interface, debug, multiprocessor system-on-chip
34	Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi	Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.	SAMOS	2009	DBLP DOI BibTeX RDF
34	Leandro Fiorin, Slobodan Lukovic, Gianluca Palermo	Implementation of a reconfigurable data protection module for NoC-based MPSoCs.	IPDPS	2008	DBLP DOI BibTeX RDF
34	Love Singhal, Elaheh Bozorgzadeh	Process variation aware system-level task allocation using stochastic ordering of delay distributions.	ICCAD	2008	DBLP DOI BibTeX RDF
34	Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross	Proactive temperature balancing for low cost thermal management in MPSoCs.	ICCAD	2008	DBLP DOI BibTeX RDF
34	Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal	Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.	DATE	2007	DBLP DOI BibTeX RDF
34	Woo-Chul Jeun, Soonhoi Ha	Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS.	ASP-DAC	2007	DBLP DOI BibTeX RDF	hardware semaphores, parallel programming, OpenMP, shared memory system, multiprocessor system-on-chip
34	Akash Kumar 0001, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal	Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.	FPL	2007	DBLP DOI BibTeX RDF
34	Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang	Reliable multiprocessor system-on-chip synthesis.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	synthesis, multiprocessor system-on-chip, thermal
34	Chong Sun, Li Shang, Robert P. Dick	Three-dimensional multiprocessor system-on-chip thermal optimization.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	synthesis, 3D, multiprocessor system-on-chip, thermal
34	Akira Yamawaki 0002, Masahiko Iwane	An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.	ICPADS	2007	DBLP DOI BibTeX RDF
34	Jaehwan John Lee, Vincent John Mooney	A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip
34	Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen	A Traffic Injection Methodology with Support for System-Level Synchronization.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
34	Jaehwan John Lee, Vincent John Mooney III	A novel O(n) parallel banker's algorithm for System-on-a-Chip.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava	Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software.	DATE	2004	DBLP DOI BibTeX RDF
34	Kai Richter 0001, Razvan Racu, Rolf Ernst	Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC.	RTSS	2003	DBLP DOI BibTeX RDF
32	Nicolas Ventroux, Alexandre Guerre, Tanguy Sassolas, L. Moutaoukil, Guillaume Blanc, Charly Bechara, Raphaël David	SESAM: An MPSoC Simulation Environment for Dynamic Application Processing.	CIT	2010	DBLP DOI BibTeX RDF	SESAM, simulation, modeling, multiprocessor, dynamic, exploration, SystemC, MPSoC
32	Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini	Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	real-time, variability, mpsoc, energy minimization
32	Zheng Liu, Jueping Cai, Ming Du, Lei Yao, Zan Li	Hybrid Communication Reconfigurable Network on Chip for MPSoC.	AINA	2010	DBLP DOI BibTeX RDF	HCR-NoC, low power, interconnection, MPSoC