Search results for "NIOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Omar A. Al Rayahi, Mohammed A. S. Khalid	UWindsor Nios II: A soft-core processor for design space exploration.	EIT	2009	DBLP DOI BibTeX RDF
94	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
78	Willian dos Santos Lima, Renata Spolon Lobato, Aleardo Manacero, Roberta Spolon Ulson	Towards a Java bytecodes compiler for Nios II soft-core processor.	ISCC	2009	DBLP DOI BibTeX RDF
61	Eugene Hyun, Mihai Sima, Michael McGuire	Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor.	CCECE	2006	DBLP DOI BibTeX RDF
49	Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown	Experiences with Soft-Core Processor Design.	IPDPS	2005	DBLP DOI BibTeX RDF
45	Abel G. Silva-Filho, Sidney M. L. Lima	Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor.	SoCC	2008	DBLP DOI BibTeX RDF
45	Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne	Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing.	ESTIMedia	2005	DBLP DOI BibTeX RDF
45	P. Moore, Máire McLoone, Sakir Sezer	Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor.	AICT/SAPIR/ELETE	2005	DBLP DOI BibTeX RDF
45	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
33	Shiuh-Jer Huang, Shian-Shin Wu	Vision-Based Robotic Motion Control for Non-autonomous Environment.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system
33	Christian Schäck, Wolfgang Heenes, Rolf Hoffmann	A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA.	SAMOS	2009	DBLP DOI BibTeX RDF	Global Cellular Automata, FPGA, multiprocessor architecture, omega network
33	Mihai Sima, Michael McGuire	Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels.	SiPS	2007	DBLP DOI BibTeX RDF
33	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
33	Ambrose Chu, Mihai Sima	Reconfigurable RSA Cryptography for Embedded Devices.	CCECE	2006	DBLP DOI BibTeX RDF
33	Ian D. L. Anderson, Mohammed A. S. Khalid	Design Space Exploration using Parameterized Cores: A Case Study.	CCECE	2006	DBLP DOI BibTeX RDF
33	Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, Hervé Levi	HW/SW Codesign of the H.263 Video Coder.	CCECE	2006	DBLP DOI BibTeX RDF
33	Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan	Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors.	DELTA	2006	DBLP DOI BibTeX RDF
33	Maya B. Gokhale, Janette Frigo, Kevin McCabe, James Theiler, Christophe Wolinski, Dominique Lavenier	Experience with a Hybrid Processor: K-Means Clustering.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	configurable system on a chip, CSOC, Excalibur, FPGA, image processing, k-means clustering
28	Zhong-xun Wang, Kai-yue Sha, Xinglong Gao	Digital Image Encryption Test System Based on FPGA and Nios II Soft Core.	Autom. Control. Comput. Sci.	2021	DBLP DOI BibTeX RDF
28	Aleieldin Shamseldin, Hassan Soubra, Reham Elnabawy	Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II.	ICM	2021	DBLP DOI BibTeX RDF
28	Argirios Sideris, Theodora Sanida, Minas Dasygenis	Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor.	MOCAST	2019	DBLP DOI BibTeX RDF
28	Zouhir Irki, Abdelhai Lati, Samir Sakhi, Abdelkrim Nemra, Mustapha Hamerlain	FPGA implementation of the RANSAC based image mosaicing algorithm using the Nios II softcore.	IWSSIP	2016	DBLP DOI BibTeX RDF
28	Naraig Manjikian	Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor.	CCECE	2016	DBLP DOI BibTeX RDF
28	Julio C. Sosa, Iván Dominguez-Lopez, Adrián L. García-García, J. D. Oscar Barceinas-Sánchez, Anuar Jassen	Sistema embebido para la detección de luz láser empleando el soft-core Nios II.	Res. Comput. Sci.	2015	DBLP BibTeX RDF
28	Chung-Wen Hung, Ke-Cheng Huang, Yan-Ting Yu, Hsuan-Ting Chang	A Nios-based colonoscopy navigation system.	Artif. Life Robotics	2015	DBLP DOI BibTeX RDF
28	Diego González 0002, Guillermo Botella, Carlos García 0001, Anke Meyer-Bäse, Uwe Meyer-Bäse, Manuel Prieto-Matías	Customized Nios II multi-cycle instructions to accelerate block-matching techniques.	Real-Time Image and Video Processing	2015	DBLP DOI BibTeX RDF
28	Vahid Rashtchi, Mohsen Nourazar	A Multiprocessor Nios II Implementation of Duffing oscillator Array for Weak signal Detection.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
28	Trifon Trifonov	IP design for DIF, integrated in Nios II systems: averaging filter.	CompSysTech	2014	DBLP DOI BibTeX RDF
28	John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill	Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding.	Int. J. Reconfigurable Comput.	2013	DBLP DOI BibTeX RDF
28	Diego González 0002, Guillermo Botella, Carlos García 0001, Manuel Prieto 0001, Francisco Tirado	Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor.	EURASIP J. Adv. Signal Process.	2013	DBLP DOI BibTeX RDF
28	A. D. Voykin, Francis Minhthang Bui, R. J. Bolton	FPGA based reconfigurable body area network using Nios II and uClinux.	CCECE	2013	DBLP DOI BibTeX RDF
28	Diego González 0002, Guillermo Botella, Uwe Meyer-Baese, Carlos García 0001, Concepción Sanz, Manuel Prieto-Matías, Francisco Tirado	A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor.	Sensors	2012	DBLP DOI BibTeX RDF
28	Lucile Senn, Eric Senn, Christian Samoyeau	Modelling the Power and Energy Consumption of NIOS II Softcores on FPGA.	CLUSTER Workshops	2012	DBLP DOI BibTeX RDF
28	Tércio A. Santos Filho	Desenvolvimento de um nó de rede com diferentes interfaces de acordo com o padrão IEEE 1451 utilizando o processador nios II e o sistema operacional embarcado uclinux.		2012	RDF
28	M. E. Paramasivam, R. S. Sabeenian	Handloom Silk Fabric Defect Detection Using First Order Statistical Features on a NIOS II Processor.	ICT	2010	DBLP DOI BibTeX RDF
28	Philipp Digeser, Marco Tubolino, Martin Klemm, Daniel Shapiro, Miodrag Bolic	Instruction set extension in the NIOS II: A floating point divider for complex numbers.	CCECE	2010	DBLP DOI BibTeX RDF
28	Hao-Chung Shih, Chian C. Ho	Soft DSP Design Methodology of Face Recognition System on Nios II Embedded Platform.	IAS	2009	DBLP DOI BibTeX RDF
28	Haimeng Zhao, Xifeng Zheng, Weiya Liu	Intelligent Traffic Control System Based on DSP and Nios II.	CAR	2009	DBLP DOI BibTeX RDF
28	Nivedita N. Joshi, P. K. Dakhole, P. P. Zode	Embedded Web Server on Nios II Embedded FPGA Platform.	ICETET	2009	DBLP DOI BibTeX RDF
28	Yang Xu, Min Xiang	Design a New Type PWM Peripherals in Nios II.	CSIE (2)	2009	DBLP DOI BibTeX RDF
28	David M. Cambre, Eduardo I. Boemo, Elias Todorovich	Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor.	ReConFig	2008	DBLP DOI BibTeX RDF	energy evaluation, embedded processor
28	Feng Lin, Haili Wang, Jinian Bian	HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design.	FPT	2005	DBLP BibTeX RDF
28	Haichen Ren, David Jeff Jackson	Morphological Image Processing Using Custom Instructions on Distributed Nios Processors.	CATA	2004	DBLP BibTeX RDF
28	Ziting Wang, Cunfang Zheng	Research of Image Capturing and Processing System Based on SOPC Technology.	NCM	2009	DBLP DOI BibTeX RDF	System on Programmable Chip, Nios II, Field Programmable Gate Arrays, Image Processing, Image Capturing
28	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
28	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
16	Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux	Vector Processing as a Soft Processor Accelerator.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
16	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
16	Michael Dyer, Saeid Nooshabadi, David S. Taubman	Design and Analysis of System on a Chip Encoder for JPEG2000.	IEEE Trans. Circuits Syst. Video Technol.	2009	DBLP DOI BibTeX RDF
16	Hui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung	Efficient K-Means VLSI Architecture for Vector Quantization.	SCIA	2009	DBLP DOI BibTeX RDF
16	Chi-Tai Cheng, Yu-Ting Yang, Shih-Heng Miao, Ching-Chang Wong	Motion and Emotional Behavior Design for Pet Robot Dog.	FIRA	2009	DBLP DOI BibTeX RDF	Robot Dog, Emotional Behavior
16	Yu-Te Su, Chun-Yang Hu, Tzuu-Hseng S. Li	FPGA-Based Vocabulary Recognition Module for Humanoid Robot.	FIRA	2009	DBLP DOI BibTeX RDF	FPGA-based, humanoid robot
16	Hui-Ya Li, Yao-Jung Yeh, Wen-Jyi Hwang, Cheng-Tsun Yang	High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware.	IEA/AIE	2009	DBLP DOI BibTeX RDF
16	Pierre-Alain Fouque, Gaëtan Leurent, Denis Réal, Frédéric Valette	Practical Electromagnetic Template Attack on HMAC.	CHES	2009	DBLP DOI BibTeX RDF
16	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
16	Yvan Eustache, Jean-Philippe Diguet	Specification and OS-based implementation of self-adaptive, hardware/software embedded systems.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	self-adaptive embedded systems, HW/SW codesign
16	Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe	A Multiprocessor System for a Small Size Soccer Robot Control System.	DELTA	2008	DBLP DOI BibTeX RDF	MP, FPGA, multiprocessor, soccer robot
16	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Exploration and Customization of FPGA-Based Soft Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Michael Dyer, Saeid Nooshabadi, David S. Taubman	Analysis of Multiple Parallel Block Coding in JPEG2000.	ICIP (5)	2007	DBLP DOI BibTeX RDF
16	Ari Kulmala, Erno Salminen, Timo D. Hämäläinen	Evaluating Large System-on-Chip on Multi-FPGA Platform.	SAMOS	2007	DBLP DOI BibTeX RDF
16	Stevan M. Bererber, Chih-Hong Wang, Kevin K. Wei	Design of a CDMA System in FPGA Technology.	VTC Spring	2007	DBLP DOI BibTeX RDF
16	Gerald Hempel, Christian Hochberger	A resource optimized Processor Core for FPGA based SoCs.	DSD	2007	DBLP DOI BibTeX RDF
16	Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusébio de Lima	Aquarius: a dynamically reconfigurable computing platform.	SBCCI	2007	DBLP DOI BibTeX RDF	?CLinux, FPGAs, prototyping, dynamic reconfiguration, tasks scheduling, device driver, bitstream
16	Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch	Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
16	V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar	SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel	A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.	ISVLSI	2006	DBLP DOI BibTeX RDF
16	Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications.	DATE	2006	DBLP DOI BibTeX RDF
16	Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel	Efficient architecture for Reed Solomon block turbo code.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle	Model of a true random number generator aimed at cryptographic applications.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Adriel Cheng, Atanas N. Parashkevov, Cheng-Chew Lim	Coverage Measurement for Software Application Testing using Partially Ordered Domains and Symbolic Trajectory Evaluation Techniques.	DELTA	2006	DBLP DOI BibTeX RDF
16	Jing Ma 0006, Xinming Huang 0001	A System-on-Programmable Chip Approach for MIMO Sphere Decoder.	FCCM	2005	DBLP DOI BibTeX RDF
16	H. G. Epassa, François R. Boyer, Yvon Savaria	Implementation of a cycle by cycle variable speed processor.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
16	Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang	Application-specific instruction generation for configurable processor architectures.	FPGA	2004	DBLP DOI BibTeX RDF	binate covering, compilation, ASIP, technology mapping, configurable processor
16	Jian Liang, Russell Tessier, Dennis Goeckel	A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.	FCCM	2004	DBLP DOI BibTeX RDF
16	Deepak Boppana, Kully Dhanoa, Jesse Kempa	FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm.	FCCM	2004	DBLP DOI BibTeX RDF
16	Martin Simka, Viktor Fischer, Milos Drutarovský	Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study.	FPL	2003	DBLP DOI BibTeX RDF
16	Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau	Interface Synthesis using Memory Mapping for an FPGA Platform.	ICCD	2003	DBLP DOI BibTeX RDF
16	Sylvain Poussier, Hassan Rabah, Serge Weber	SOPC-based Embedded Smart Strain Gage Sensor.	FPL	2002	DBLP DOI BibTeX RDF