Search results for "PC-RAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Tia Newhall, Daniel Amato, Alexandr Pshenichkin	Reliable adaptable Network RAM.	CLUSTER	2008	DBLP DOI BibTeX RDF
83	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
81	Manoj Franklin, Kewal K. Saluja	Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
78	Miklós Ajtai	Oblivious RAMs without cryptogrpahic assumptions.	STOC	2010	DBLP DOI BibTeX RDF	RAM, oblivious
76	Juraj Wiedermann	Normalizing and Accelerating RAM Computations and the Problem of Reasonable Space Measures.	ICALP	1990	DBLP DOI BibTeX RDF
68	Aviad Zuck, Ohad Barzilay, Sivan Toledo	NANDFS: a flexible flash file system for RAM-constrained systems.	EMSOFT	2009	DBLP DOI BibTeX RDF	RAM constrained, page mapping, file system, flash, NAND flash
68	In Hwan Doh, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh	Exploiting non-volatile RAM to enhance flash file system performance.	EMSOFT	2007	DBLP DOI BibTeX RDF	non-volatile RAM, metadata, file system, flash memory, experimental evaluation
68	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
68	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
68	Li Xiao 0001, Xiaodong Zhang 0001, Stefan A. Kubricht	Incorporating Job Migration and Network RAM to Share Cluster Memory Resources.	HPDC	2000	DBLP DOI BibTeX RDF
62	Alejandro López-Ortiz, Mehdi Mirzazadeh, Mohammad Ali Safari, M. Hossein Sheikh Attar	Fast string sorting using order-preserving compression.	ACM J. Exp. Algorithmics	2005	DBLP DOI BibTeX RDF	Order-preserving compression, unit-cost RAM, sorting, word-RAM
62	Swapan Kumar Ray	Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Content Addressable Memory (CAM), associative store, Associative Memory (AM), pipelined CAM, Content-To-Address Memory (CTAM), pipelined CTAM, Binary Search Processor (BSP), Pipelined Binary Search Processor (PBSP), pipelined binary search, Binary Search Pipeline (BSPL), pipelined search processor, pipelined search engine
60	Torben Hagerup	Sorting and Searching on the Word RAM.	STACS	1998	DBLP DOI BibTeX RDF	word-level parallelism, exponential range reduction, fusion trees, exponential search trees, AC', searching, Sorting, network flow, multiplication, dictionaries, tries, word RAM, conservative algorithms
60	Naoto Takahashi, Atsushi Kameda, Masahito Yamamoto, Azuma Ohuchi	Aqueous Computing with DNA Hairpin-Based RAM.	DNA	2004	DBLP DOI BibTeX RDF
60	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-based FPGA's: testing the LUT/RAM modules.	ITC	1998	DBLP DOI BibTeX RDF
53	An-I Andy Wang, Geoffrey H. Kuenning, Peter L. Reiher, Gerald J. Popek	The Conquest file system: Better performance through a disk/persistent-RAM hybrid design.	ACM Trans. Storage	2006	DBLP DOI BibTeX RDF	Persistent RAM, performance measurement, file systems, storage management
52	Nathan Cooprider, John Regehr	Offline compression for on-chip ram.	PLDI	2007	DBLP DOI BibTeX RDF	sensor networks, static analysis, data compression, embedded software, TinyOS, memory optimization
52	Raphael V. Carneiro, Stiven Schwanz Dias, Dijalma Fardin, Hallysson Oliveira, Artur S. d'Avila Garcez, Alberto Ferreira de Souza	Improving VG-RAM Neural Networks Performance Using Knowledge Correlation.	ICONIP (1)	2006	DBLP DOI BibTeX RDF
52	Lei Yang 0017, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar	CRAMES: compressed RAM for embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	embedded system, compression, memory
52	Mohammed Sayed, Wael M. Badawy	A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications.	IWSOC	2003	DBLP DOI BibTeX RDF
52	Etienne Grandjean, J. M. Robson	RAM with Compact Memory: A Realistic and Robust Model of Computation.	CSL	1990	DBLP DOI BibTeX RDF
46	Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli	Exploiting Transition Locality in the Disk Based Mur phi Verifier.	FMCAD	2002	DBLP DOI BibTeX RDF
45	Manoj Franklin, Kewal K. Saluja	Hypergraph Coloring and Reconfigured RAM Testing.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
45	Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002	Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	STT-RAM, emerging memory, spintronic
45	Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang	The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection.	CCTA	2007	DBLP DOI BibTeX RDF	dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication
45	Michel Renovell, Joan Figueras, Yervant Zorian	Test of RAM-based FPGA: methodology and application to the interconnect.	VTS	1997	DBLP DOI BibTeX RDF	RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
45	Alberto Ferreira de Souza, Claudine Badue, Felipe Pedroni, Elias Oliveira, Stiven Schwanz Dias, Hallysson Oliveira, Sotério Ferreira de Souza	Face Recognition with VG-RAM Weightless Neural Networks.	ICANN (1)	2008	DBLP DOI BibTeX RDF
45	Rui Chu, Nong Xiao, Xicheng Lu	A Resource Information Management System for RAM Grid.	GCC	2007	DBLP DOI BibTeX RDF
45	Vassil Roussev, Golden G. Richard III, Daniel Tingstrom	dRamDisk: efficient RAM sharing on a commodity cluster.	IPCCC	2006	DBLP DOI BibTeX RDF
45	Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J. Cohen, Steve Merrill, Ramesh Durairaj, Paul Daspit, Inder Monga, Sumit Naiksatam, Silvia M. Figueira, David Gutierrez, Doan B. Hoang, Franco Travostino	DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks.	CCGRID	2004	DBLP DOI BibTeX RDF
45	Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas	Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
45	Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie	Computational RAM: Implementing Processors in Memory.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
45	Manoj Sachdev	Reducing the CMOS RAM test complexity withIDDQ and voltage testing.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	fault model, faults, defects, March test, I DDQ testing
45	Jop F. Sibeyn, Tim J. Harris	Exploiting Locality in LT-RAM Computations.	SWAT	1994	DBLP DOI BibTeX RDF
40	Betty Prince	Embedded non-volatile memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM
39	John Oleszkiewicz, Li Xiao 0001, Yunhao Liu 0001	Effectively Utilizing Global Cluster Memory for Large Data-Intensive Parallel Programs.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	network RAM, simulation, cluster, scheduling, peer-to-peer, Parallel programs
39	Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao	An energy efficient TLB design methodology.	ISLPED	2005	DBLP DOI BibTeX RDF	Godson-I, embedded processor design, single-port RAM, energy efficient, TLB, low-power consumption
39	Kuo-Su Hsiao, Chung-Ho Chen	An efficient wakeup design for energy reduction in high-performance superscalar processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	issue window, wakeup logic, low power, high performance
39	Li Xiao 0001, Songqing Chen, Xiaodong Zhang 0001	Adaptive Memory Allocations in Clusters to Handle Unexpectedly Large Data-Intensive Jobs.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF
39	Yiming Hu, Tycho Nightingale, Qing Yang 0001	RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage Systems.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	fault-tolerance, performance, reliability, storage systems, disks
37	Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili	An energy efficient cache design using spin torque transfer (STT) RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	(STT)RAM, memory technologies, cache design
37	Hong-Hee Lee, Hoang M. Nguyen	Implementation of Induction Motor Control System Using Matrix Converter Based on CAN Network and Dual-Port RAM.	ICIC (2)	2009	DBLP DOI BibTeX RDF	CAN network, dual-port RAM, Matrix converter
37	Chie Dou, Shing-Jeh Jiang, Kuo-Cheng Leu	A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers.	DELTA	2002	DBLP DOI BibTeX RDF	CAM/RAM integration, buffer manager, content addressable memory, IP router
37	Marc D. Riedel, Janusz Rajski	Fault coverage analysis of RAM test algorithms.	VTS	1995	DBLP DOI BibTeX RDF	RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
37	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
37	Xuejun Yang, Nathan Cooprider, John Regehr	Eliminating the call stack to save RAM.	LCTES	2009	DBLP DOI BibTeX RDF	stack liveness, sensor networks, compiler optimization, embedded software, memory allocation, memory optimizations
37	Claudine Badue, Felipe Pedroni, Alberto Ferreira de Souza	Multi-label Text Categorization Using VG-RAM Weightless Neural Networks.	SBRN	2008	DBLP DOI BibTeX RDF
37	Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy	Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
37	Rui Chu, Jiancong Xie, Nong Xiao, Xicheng Lu	RAM Grid Middleware for Autonomic Cooperative Caching.	GCC	2007	DBLP DOI BibTeX RDF
37	Min-Sik Jin, Min-Soo Jung	A Study on Fast JCVM by Moving Object from EEPROM to RAM.	RTCSA	2005	DBLP DOI BibTeX RDF
37	Ran Mendelson, Mikkel Thorup, Uri Zwick	Meldable RAM priority queues and minimum directed spanning trees.	SODA	2004	DBLP BibTeX RDF
37	Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli	Integrating RAM and Disk Based Verification within the Mur-phi Verifier.	CHARME	2003	DBLP DOI BibTeX RDF
37	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
37	Nils Maltesson, David Naccache, Elena Trichina, Christophe Tymen	Applet Verification Strategiesfor RAM-Constrained Devices.	ICISC	2002	DBLP DOI BibTeX RDF
37	Stamatios V. Kartalopoulos	An associative RAM-based CAM and its application to broadband communications systems.	IEEE Trans. Neural Networks	1998	DBLP DOI BibTeX RDF
37	Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal	Initializing RAM-based logarithmic processors.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
37	Nader H. Bshouty	Lower Bounds for the Complexity of Functions in a Realistic RAM Model.	ISTCS	1992	DBLP DOI BibTeX RDF
37	Ashok K. Goel 0002, Apurva Kalia	Simulation of ram-based asynchronous sequential circuits.	Annual Simulation Symposium	1990	DBLP DOI BibTeX RDF
32	Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu	Simulation-Based Test Algorithm Generation for Random Access Memories.	VTS	2000	DBLP DOI BibTeX RDF	RAM fault simulation, March test algorithm, Cocktail-March test algorithms, semiconductor memories, RAM testing
32	Yuejian Wu, Sanjay Gupta	Built-In Self-Test for Multi-Port RAMs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
32	Kewal K. Saluja	On-chip testing of random access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
32	Bowen Alpern, Larry Carter, Ephraim Feig	Uniform Memory Hierarchies	FOCS	1990	DBLP DOI BibTeX RDF	RAM complexity, uniform memory hierarchy, computer memory, FFT programs, parallelism, RAM, parsimonious, random-access-machine
32	Vason P. Srini	Fault Location in a Semiconductor Random-Access Memory Unit.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Cables, controlled register, RAM chip, RAM unit, fault model, fault location, test sequence
31	Ilya Baran, Erik D. Demaine, Mihai Patrascu	Subquadratic Algorithms for 3SUM.	Algorithmica	2008	DBLP DOI BibTeX RDF	3SUM, Randomization, Word RAM
31	Anne M. P. Canuto, Gareth Howells 0001, Michael C. Fairhurst	An Investigation of the Effects of Variable Vigilance within the RePART Neuro-Fuzzy Network.	J. Intell. Robotic Syst.	2000	DBLP DOI BibTeX RDF	reward/punishment parameter, RePART, fuzzy multi-layer perceptron, radial RAM, variable vigilance parameter, fuzzy ARTMAP, handwritten numeral recognition
31	Lizyamma Kurian, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
31	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
31	Xi Chen, Prateek Gangwal, Daji Qiao	Practical Rate Adaptation in Mobile Environments.	PerCom	2009	DBLP DOI BibTeX RDF
31	Jörg Kienzle, Wisam Al Abed, Jacques Klein	Aspect-oriented multi-view modeling.	AOSD	2009	DBLP DOI BibTeX RDF	aspect dependencies, binding, class diagram, sequence diagram, aspect-oriented modeling, state diagram, instantiation
31	Ann M. Bouchard, Gordon C. Osbourn	Dynamic self-assembly in living systems as computation.	Nat. Comput.	2006	DBLP DOI BibTeX RDF	biological information processing, microtubule, motor protein, protein network, unary number, algorithm, computation, computing, information, self-assembly, stochastic, random access machine
31	Li-Pin Chang, Tei-Wei Kuo	Efficient management for large-scale flash-memory storage systems with resource conservation.	ACM Trans. Storage	2005	DBLP DOI BibTeX RDF	embedded systems, memory management, Flash memory, storage systems, consumer electronics, portable devices
31	Seung-Joon Seok, Seok-Min Hong, Sung-Hyuck Lee, Chul-Hee Kang	A Dynamic Marking Scheme of Assured Service for Alleviating Unfairness among Service Level Agreements.	MMNS	2002	DBLP DOI BibTeX RDF
31	Seung-Joon Seok, Sung-Hyuck Lee, Seok-Min Hong, Chul-Hee Kang	Unfairness of Assured Service and a Rate Adaptive Marking Strategy.	QofIS	2002	DBLP DOI BibTeX RDF
31	Paolo Gai, Giuseppe Lipari, Marco Di Natale	Minimizing Memory Utilization of Real-Time Task Sets in Single and Multi-Processor Systems-on-a-Chip.	RTSS	2001	DBLP DOI BibTeX RDF
31	Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik	Computational power of pipelined memory hierarchies.	SPAA	2001	DBLP DOI BibTeX RDF
31	Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley	A Multi-Level Memory System Architecture for High-Performance DSP Applications.	ICCD	2000	DBLP DOI BibTeX RDF
31	Yiming Hu, Qing Yang 0001, Tycho Nightingale	RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems.	HPCA	1999	DBLP DOI BibTeX RDF
31	Oded Goldreich 0001, Rafail Ostrovsky	Software Protection and Simulation on Oblivious RAMs.	J. ACM	1996	DBLP DOI BibTeX RDF	simulation of random access machines, software protection, pseudorandom functions
31	Xiao-ping Ling, Hideharu Amano	Performance evaluation of WASMII: a data driven computer on a virtual hardware.	PARLE	1993	DBLP DOI BibTeX RDF
31	Rafail Ostrovsky	An Efficient Software Protection Scheme.	CRYPTO	1989	DBLP DOI BibTeX RDF
29	Tia Newhall, Douglas Woos	Incorporating Network RAM and Flash into Fast Backing Store for Clusters.	CLUSTER	2011	DBLP DOI BibTeX RDF	Network RAM, cluster backing store, flash
29	Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho	A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications.	DAC	2006	DBLP DOI BibTeX RDF	DVD-RAM, SATA, WSR, CMOS, optical storage
29	Kanad Chakraborty, Pinaki Mazumder	New March Tests for Multiport RAM Devices.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults
29	B. Suresh, Biswadeep Chaterjee, R. Harinath	Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability
29	Trevor G. Clarkson, Denise Gorse, John G. Taylor, C. K. Ng	Learning Probabilistic RAM Nets Using VLSI Structures.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	synaptic noise, global rewards, global penalties, local penalties, RAM nets, VLSI structures, learning probabilistic RAMs, local reinforcement rules, local rewards, serial updating, VLSI, neural nets, backpropagation, backpropagation, weights, content-addressable storage, stochastic search, learning rule
29	René David, Antoine Fuentes	Fault Diagnosis of RAM's from Random Testing Experiments.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	random testing experiments, fault diagnosis, simulation results, fault location, random-access storage, RAM
29	Eric Regener	A Transition Sequence Generator for RAM Fault Detection.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	transition sequence generator, RAM fault detection, n-bit CMOS memories, test address sequence, ordered pair, next-state generator, integrated circuit testing, logic circuit, CMOS integrated circuits, random-access storage, integrated memory circuits
29	Petra De Jong, Ad J. van de Goor	Test Pattern Generation for API Faults in RAM.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	API faults, near optimal WRITE sequence, integrated circuit testing, BIST, automatic testing, fault location, test pattern generation, Hamiltonian paths, random-access storage, RAM, integrated memory circuits, pattern-sensitive faults
29	Thomas E. Fuja, Chris Heegard	Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	hard defects, RAM's, row/column replacement, reliability, redundancy, Error-control coding, yield improvement
29	Shalhav Zohar	A Realization of the RAM Digital Filter.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	hardware digital filter, negative radix application, RAM digital filter, real-time digital filter, Digital filter
29	Shijie Zhang, Jiong Yang 0001	RAM: Randomized Approximate Graph Mining.	SSDBM	2008	DBLP DOI BibTeX RDF
29	Rui Chu, Nong Xiao, Lei Chen 0002, Xicheng Lu	A push-based prefetching for cooperative caching RAM Grid.	ICPADS	2007	DBLP DOI BibTeX RDF
29	Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache	Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.	IOLTS	2007	DBLP DOI BibTeX RDF
29	Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy	Power-aware RAM mapping for FPGA embedded memory blocks.	FPGA	2006	DBLP DOI BibTeX RDF	embedded memory block, FPGA, dynamic power
29	Dongming Peng, Mi Lu	Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
29	Ghenadie Bodean, Diana Bodean, A. Labunetz	New Schemes for Self-Testing RAM.	DATE	2005	DBLP DOI BibTeX RDF
29	Subhasis Bhattacharjee, Dhiraj K. Pradhan	LPRAM: a novel low-power high-performance RAM design with testability and scalability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
29	Gaoxiang Ouyang, Xiaoli Li 0002, Xinping Guan, Zhiqiang Zhang, Xiuling Zhang, Ruxu Du	Ram Velocity Control in Plastic Injection Molding Machines with Neural Network Learning Control.	ISNN (2)	2004	DBLP DOI BibTeX RDF
29	Rui-fang Liu, Changsheng Xie, Zhi-hu Tan, Qing Yang 0001	A New Hierarchy Cache Scheme Using RAM and Pagefile.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
29	Silvia M. Figueira, Sumit Naiksatam, Howard J. Cohen, Doug Cutrell, Paul Daspit, David Gutierrez, Doan B. Hoang, Tal Lavian, Joe Mambretti, Steve Merrill, Franco Travostino	DWDM-RAM: enabling Grid services with dynamic optical networks.	CCGRID	2004	DBLP DOI BibTeX RDF