Search results for "PLDs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Michael D. Hutton	Interconnect prediction for programmable logic devices.	SLIP	2001	DBLP DOI BibTeX RDF	interconnect prodiction, wireability, architecture, programmable logic device
75	Dewayne E. Perry, Jeff Kramer	Architectural Description.	ESPRIT ARES Workshop	1998	DBLP DOI BibTeX RDF
56	Maurice Gagnaire, Mohamed Koubàa, Nicolas Puech	Network Dimensioning under Scheduled and Random Lightpath Demands in All-Optical WDM Networks.	IEEE J. Sel. Areas Commun.	2007	DBLP DOI BibTeX RDF
56	A. Abo Shosha, P. Reinhart, F. Rongen	Reconfigurable PCI-Bus Interface (RPCI).	FPL	1998	DBLP DOI BibTeX RDF
48	Snezhana P. Kostova	A PLDS Model of Pollution in Connected Water Reservoirs.	POSTA	2003	DBLP DOI BibTeX RDF
48	Eric W. Johnson	Extensive Introduction to VHDL and PLDs in the Sophomore Year.	MSE	2003	DBLP DOI BibTeX RDF
48	Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio	TOP: An Algorithm for Three-Level Optimization of PLDs.	DATE	2000	DBLP DOI BibTeX RDF
48	Jason Helge Anderson, Stephen Dean Brown	Technology Mapping for Large Complex PLDs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
48	Niklaus Wirth	The Language Lola, FPGAs and PLDs in Teaching Digital Circuit Design.	Ershov Memorial Conference	1996	DBLP DOI BibTeX RDF
38	Adrian J. Hilton, Jon G. Hall	High-Integrity Interfacing to Programmable Logic with Ada.	Ada-Europe	2004	DBLP DOI BibTeX RDF
38	Valeri Tomachev	The PLD-Implementation of Boolean Function Characterized by Minimum Delay.	FPL	1998	DBLP DOI BibTeX RDF
33	Wenyi Feng, Sinan Kaptanoglu	Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
33	Wenyi Feng, Sinan Kaptanoglu	Designing efficient input interconnect blocks for LUT clusters using counting and entropy.	FPGA	2007	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
29	Chaofeng Yuan, Yuelei Xu, Qing Zhou	PLDS-SLAM: Point and Line Features SLAM in Dynamic Environment.	Remote. Sens.	2023	DBLP DOI BibTeX RDF
29	Karnika Shivhare, Rushikesh K. Joshi	Process Line Diagrams (PLDs): An Approach for Modular Process Modeling.	ISEC	2023	DBLP DOI BibTeX RDF
29	Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque	Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison.	ISCAS	2019	DBLP DOI BibTeX RDF
29	Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana	Programmable Logic Devices (PLDs) in Practical Applications.	Principles and Structures of FPGAs	2018	DBLP DOI BibTeX RDF
29	Tommaso Addabbo, Ada Fort, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque	Digital Nonlinear Oscillators in PLDs: Pitfalls and Open Perspectives for a Novel Class of True Random Number Generators.	ISCAS	2018	DBLP DOI BibTeX RDF
29	G. Sumathi, L. Srivani, D. Thirugnana Murthy, Anish Kumar, K. Madhusoodanan	Hardware Obfuscation Using Different Obfuscation Cell Structures for PLDs.	SG-CRC	2017	DBLP DOI BibTeX RDF
29	Hiroki Nishiyama 0003, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko	An ILP-Based Optimal Circuit Mapping Method for PLDs.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
29	Marian Gilewski	An Application of PLDs in Diode Laser Drivers.	PDeS	2013	DBLP DOI BibTeX RDF
29	Min Feng 0001, Changhui Lin, Rajiv Gupta 0001	PLDS: Partitioning linked data structures for parallelism.	ACM Trans. Archit. Code Optim.	2012	DBLP DOI BibTeX RDF
29	Bashar Al-Khalifa	A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs.	Int. Arab J. Inf. Technol.	2010	DBLP BibTeX RDF
29	Monica Figueiredo, Rui L. Aguiar	Performance of 155Mbps clock/data recovery circuits on heavy loaded PLDs.	ICECS	2003	DBLP DOI BibTeX RDF
29	Guy G. Lemieux, Paul Leventis, David M. Lewis	Generating highly-routable sparse crossbars for PLDs.	FPGA	2000	DBLP DOI BibTeX RDF
29	Jason Cong, Songjie Xu	Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs.	ASP-DAC	2000	DBLP DOI BibTeX RDF
29	Alan E. Clapp, Thomas L. Harman	Combining microcontroller units and PLDs for best system design.	IEEE Micro	1994	DBLP DOI BibTeX RDF
29	André Klindworth	A Tool-Set for Simulating Altera-PLDs Using VHDL.	FPL	1994	DBLP DOI BibTeX RDF
29	Martin Bolton	Practical Programmable Circuits: A Guide to PLDs, State Machines and Microcontrollers: James D Broesch Academic Press, London, UK (1991) ISBN 0 12 134885 7, £34, pp 286.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
29	Chris Jay	VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
29	Serafín Pérez, Enrique Mandado, Jacobo Ruiz de Ojeda	Logic controllers design methods using advanced PLDS.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
29	Günter Biehl	Overview of Complex Array-Based PLDs.	FPL	1992	DBLP DOI BibTeX RDF
29	Abdul A. Malik, David Harrison, Robert K. Brayton	Three-Level Decomposition with Application to PLDs.	ICCD	1991	DBLP DOI BibTeX RDF
19	Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi	Lions and tigers and bears: investigating cues for expressive creature motion.	SIGGRAPH Posters	2010	DBLP DOI BibTeX RDF
19	Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi	Using eye tracking to investigate important cues for representative creature motion.	ETRA	2010	DBLP DOI BibTeX RDF	point-light display, animation, perception, eyetracking
19	Hassan Farhat	Integrating electronics in computer science under curricula constraints, a comparative study.	EIT	2008	DBLP DOI BibTeX RDF
19	Jin-Wei Tioh, Rashmi Bahuguna, Nathan A. VanderHorn, Mani Mina, Robert J. Weber, Arun K. Somani	Reprogrammable high-speed platform : Bridging the gap between research, education and engineering.	EIT	2008	DBLP DOI BibTeX RDF
19	Issam W. Damaj	Higher-Level Hardware Synthesis of the KASUMI Algorithm.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel algorithms, methodology, formal models, data encryption, gate array
19	Seung-Jun Lee, Chunsoo Ahn, Jitae Shin	Control Parameter Setting of IEEE 802.11e for Proportional Loss Rate Differentiation.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
19	Sandip Kundu, T. M. Mak, Rajesh Galivanche	Trends in manufacturing test methods and their implications.	ITC	2004	DBLP DOI BibTeX RDF
19	Christian Siemers, Volker Winterstein	Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
19	Kenneth Yan	Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks.	ASP-DAC	2001	DBLP DOI BibTeX RDF
19	Artur Chojnacki, Lech Józwiak	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.	ISQED	2001	DBLP DOI BibTeX RDF
19	Artur Chojnacki, Lech Józwiak	Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures.	ISMVL	2000	DBLP DOI BibTeX RDF
19	Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung	Optimizations for a Highly Cost-Efficient Programmable Logic Architecture.	FPGA	1998	DBLP DOI BibTeX RDF
19	Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak	Design of Self-Synchronized Component FSMs for Self-Timed Systems.	EUROMICRO	1998	DBLP DOI BibTeX RDF
19	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
19	C. Hwa Chang, Hammad K. Azzam	A weighted technique for programmable logic devices minimization.	MICRO	1990	DBLP BibTeX RDF