Search results for "Prescaler"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
109	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.	SBCCI	2004	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, low power, prescaler
90	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4.1 GHz prescaler using double data throughput E-TSPC structures.	SBCCI	2007	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, prescaler
81	Quan Yuan, Haigang Yang, Fang-yuan Dong, Tao Yin	"Time borrowing" technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer.	ISCAS	2008	DBLP DOI BibTeX RDF
81	Hans-Dieter Wohlmuth, Daniel Kehrer	A 24 GHz dual-modulus prescaler in 90nm CMOS.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
81	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A new 5 GHz CMOS dual-modulus prescaler.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
81	Hong Jo Ahn, Mohammed Ismail 0001	GHz programmable dual-modulus prescaler for multi-standard wireless applications.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
66	Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.	SBCCI	2005	DBLP DOI BibTeX RDF	high speed digital circuit, low power, prescaler, frequency synthesizer
62	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures.	ISCAS	2007	DBLP DOI BibTeX RDF
62	Stephen Machan	A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18µm CMOS Technology.	IWSOC	2003	DBLP DOI BibTeX RDF
62	Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez	A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
57	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A New Phase Noise Model for TSPC based divider.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
49	No Yong Kwon, Bora Kim, Yong Moon	A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess.	ISOCC	2016	DBLP DOI BibTeX RDF
43	Keliu Shu, Edgar Sánchez-Sinencio	A 5-GHz prescaler using improved phase switching.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
43	Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost	A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology.	ISLPED	1998	DBLP DOI BibTeX RDF
38	Ko-Chi Kuo, Feng-Ji Wu	A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
38	João Navarro Jr., Wilhelmus A. M. Van Noije	Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
28	Suchitav Khadanga	Synchronous programmable divider design for PLL Using 0.18 um cmos technology.	IWSOC	2003	DBLP DOI BibTeX RDF	programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
28	Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac	Long and Fast Up/Down Counters.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Binary counter, constant time counter, serial counter, up/down counter, prescaler, parallel counter
24	Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma	A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
24	Devavarshini Arulnambi, Khutiza Afrose Syed, Yue-Fang Kuo, Po-Hsien Wu	An Efficient Architecture Design of High-Speed Dual-Modulus Prescaler for Frequency Synthesizers.	ICCE-Taiwan	2023	DBLP DOI BibTeX RDF
24	Yu Liu, Alexander C. Frank, Tilman Esslinger, Tobias Donner, Abdulkadir Akin	Laser Frequency Stabilization Using a Prescaler and a High-Resolution Frequency to Voltage Converter.	QCE	2023	DBLP DOI BibTeX RDF
24	Vasileios Chioktour, Athanasios Kakarountas	Constant delay systolic binary counter with variable size cellular automaton based prescaler.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
24	Uma Nirmal, V. K. Jain	Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology.	Int. J. Comput. Aided Eng. Technol.	2021	DBLP DOI BibTeX RDF
24	Seokwon Kang, Kyunghwan Choi, Yongjun Park 0001	PreScaler: an efficient system-aware precision scaling framework on heterogeneous systems.	CGO	2020	DBLP DOI BibTeX RDF
24	Lukas Polzin, Marcel van Delden, Nils Pohl, Klaus Aufinger, Thomas Musch	A 117 GHz Dual-Modulus Prescaler With Inductive Peaking for a Programmable Frequency Divider.	BCICTS	2020	DBLP DOI BibTeX RDF
24	Gautam R. Gangasani, Peter R. Kinget	A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
24	Suraj Kumar Saw, Madhusudan Maiti, Preetisudha Meher	Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer.	iSES	2019	DBLP DOI BibTeX RDF
24	Wenjian Jiang, Fengqi Yu, Qinjin Huang	A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
24	Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin	A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
24	Vasileios Chioktour, Georgios P. Spathoulas, Athanasios Kakarountas	Systolic Binary Counter using a Cellular Automaton-based Prescaler.	PCI	2017	DBLP DOI BibTeX RDF
24	Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang 0001	A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
24	Song Jia, Ziyi Wang, Zijin Li, Yuan Wang 0001	A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic.	ISCAS	2016	DBLP DOI BibTeX RDF
24	Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu 0011, Tao Yin, Dandan Zhang, Hongfeng Zhang	A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
24	Meilin Wan, Zhenzhen Zhang, Wang Liao, Kui Dai, Xuecheng Zou	A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
24	Song Jia, Shilin Yan, Yuan Wang 0001, Ganggang Zhang	A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic.	ISCAS	2015	DBLP DOI BibTeX RDF
24	Cristina Azcona, Belén Calvo, Nicolás Medrano, Santiago Celma, Cecilia Gimeno	A wide-range dual-modulus prescaler using a novel SCL biasing technique.	ISCAS	2015	DBLP DOI BibTeX RDF
24	Takeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima	8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler.	IEICE Trans. Electron.	2014	DBLP DOI BibTeX RDF
24	I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu	A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
24	Jianhui Wu 0001, Zixuan Wang, Xincun Ji, Cheng Huang 0005	A low-power high-speed true single phase clock divide-by-2/3 prescaler.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
24	Zheng Sun, Yong Xu, Chen Hu, Guangyan Ma, Yuanliang Wu, Ying Huang	Design of novel high speed dual-modulus prescaler based on new optimized structure.	ASICON	2013	DBLP DOI BibTeX RDF
24	Hyunchol Shin	A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
24	Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi, Kenji Kawakami, Toshiya Uozumi	Parallel Dual Modulus Prescaler with a Step Size of 0.5.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
24	Elkim Roa, Byunghoo Jung	A 50GHz 130µW inductorless prescaler in 45nm SOI CMOS using ETSPC logic.	ISCAS	2012	DBLP DOI BibTeX RDF
24	Keping Wang, Kaixue Ma, Kiat Seng Yeo	Low-power high-speed dual-modulus prescaler for Gb/s applications.	APCCAS	2012	DBLP DOI BibTeX RDF
24	Xincun Ji, Fuqing Huang, Jianhui Wu 0001, Longxing Shi	An 11.2-mW 5-GHz CMOS Frequency Synthesizer with Low Power Prescaler for Zigbee Application.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
24	Yunfeng Yu, Tianchun Ye 0001, Chengyan Ma	Optimization and design of a novel prescaler and its application to GPS receivers.	Sci. China Inf. Sci.	2011	DBLP DOI BibTeX RDF
24	Qun Jane Gu, Heng-Yu Jian, Zhiwei Xu 0003, Yi-Cheng Wu, Mau-Chung Frank Chang, Yves Baeyens, Young-Kai Chen	CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
24	Huimin Liu, Xiaoxing Zhang, Yujie Dai, Yingjie Lv	Low Power CMOS High Speed Dual-Modulus 15/16 Prescaler for Wireless Communications.	CMC	2011	DBLP DOI BibTeX RDF
24	Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim	Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
24	Seungsoo Kim, Jaewook Shin, Hyunchol Shin	On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto	A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
24	Lei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang	A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners.	ISSCC	2009	DBLP DOI BibTeX RDF
24	Yanping Ding, Kenneth K. O	A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
24	Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto	A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS.	ESSCIRC	2007	DBLP DOI BibTeX RDF
24	Yi-Shing Shih, Jenn-Hwan Tarng	A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
24	Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo	A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler.	ICECS	2006	DBLP DOI BibTeX RDF
24	Chihun Lee, Lan-chou Cho, Shen-Iuan Liu	A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.	CICC	2006	DBLP DOI BibTeX RDF
24	Ram Singh Rana	Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-μm CMOS technology.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
24	Olivier Mazouffre, Hervé Lapuyade, Jean-Baptiste Bégueret, Andreia Cathelin, Didier Belot, Yann Deval	A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler.	J. Low Power Electron.	2005	DBLP DOI BibTeX RDF
24	Rasoul Dehghani	A very low power 3ghz 128/129 CMOS dual-modulus prescaler.	ICECS	2005	DBLP DOI BibTeX RDF
24	Mihai A. T. Sanduleanu, Razvan Ionita, Andrei Vladimirescu	A 34GHz/1V prescaler in 90nm CMOS SOI.	ESSCIRC	2005	DBLP DOI BibTeX RDF
24	Huayi Zhang, Ezz I. El-Masry	A novel CMOS power efficient and glitch free d-flip-flop for dual-modulus prescaler.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
24	Chin-Sheng Chen, Robert C. Chang	A new prescaler for fully integrated 5-GHz CMOS frequency synthesizer.	ISCAS (4)	2004	DBLP BibTeX RDF
24	Ahmed Wafa, Ayman Ahmed	High-speed RF multi-modulus prescaler architecture for ΣΔ fractional-N PLL frequency synthesizers.	ISCAS (4)	2004	DBLP BibTeX RDF
24	Mark P. Houlgate, Daniel J. Olszewski, Karim Abdelhalim, Leonard MacEachern	Adaptable MOS current mode logic for use in a multi-band RF prescaler.	ISCAS (4)	2004	DBLP BibTeX RDF
24	Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi	A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
24	Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu	10 GHz quadrature-phase voltage controlled oscillator and prescaler.	ESSCIRC	2003	DBLP DOI BibTeX RDF
24	Hans-Dieter Wohlmuth, Daniel Kehrer	A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS.	ESSCIRC	2003	DBLP DOI BibTeX RDF
24	Ki-Hyuk Sung, Lee-Sup Kim	Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler".	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
24	Ayman I. Ahmed, Khalid Sharaf, Hisham S. Haddara, Hani F. Ragai	CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers.	ISCAS	2000	DBLP DOI BibTeX RDF
24	Marc Tiebout	A 480 μW 2 GHz ultra low power dual-modulus prescaler in 0.25 μm standard CMOS.	ISCAS	2000	DBLP DOI BibTeX RDF
24	Hongyan Yan, Manish Biyani, Kenneth K. O	A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	Joao Navarro Soares, Wilhelmus A. M. Van Noije	A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC).	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	W.-H. Chang, D. R. Pehlke, R. Yu	A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications.	CICC	1999	DBLP DOI BibTeX RDF
24	Abdelaziz Benachour, Sherif H. K. Embabi, Akbar Ali	A 1.5 GHz, sub-2 mW CMOS dual-modulus prescaler.	CICC	1999	DBLP DOI BibTeX RDF
24	Dirk Pfaff, Qiuting Huang	A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications.	CICC	1999	DBLP DOI BibTeX RDF
24	Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu	New dynamic flip-flops for high-speed dual-modulus prescaler.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
24	Rami Ahola, Kari Halonen	A 4 GHz CMOS multiple modulus prescaler.	ICECS	1998	DBLP DOI BibTeX RDF
24	Byungsoo Chang, Joonbae Park, Wonchan Kim	A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
24	Jan Craninckx, Michiel S. J. Steyaert	A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
24	Patrik Larsson	High-speed architecture for a programmable frequency divider and a dual-modulus prescaler.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
24	Jan Craninckx, Michel S. J. Steyaert	A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
24	Tim Seneff, Lynelle McKay, Kurt Sakamoto, Neil Tracht	A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
19	JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong Hyuk Park, Sang-Sung Choi	A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process.	DELTA	2008	DBLP DOI BibTeX RDF	single-sideband (SSB) mixer, UWB, phase-locked loop (PLL), Frequency Synthesizer
19	Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf	A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump
19	Taoufik Bourdi, Assaad Borjak, Izzet Kale	A modeling platform for efficient characterization of phase-locked loop Delta Sigma frequency synthesizers.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun	Design of A 2.4-GHz integrated frequency synthesizer.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee	A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Young-Mi Lee, Ju-Sang Lee, Sang Jin Lee, Ri-A Ju	Design of a frequency synthesizer for WCDMA in 0.18µm CMOS process.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Won Hyo Lee, Jun Dong Cho, Sung Dae Lee	A High Speed and Low Power Phase-Frequency Detector and Charge - pump.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Amr N. Hafez, Mohamed I. Elmasry	A low power monolithic subsampled phase-locked loop architecture for wireless transceivers.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
19	Rami Ahola, Kari Stadius, Kari Halonen	Design of a fully integrated 2 GHz CMOS frequency synthesizer.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
19	Juha Häkkinen, Timo Rahkonen, Juha Kostamovaara	A frequency hopping synthesizer IC for IF and RF applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF