Search results for "Processor-in-Memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Slo-Li Chu	An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture.	EUC	2005	DBLP DOI BibTeX RDF	EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory
36	Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration.	HPCA	2000	DBLP DOI BibTeX RDF	directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
35	Slo-Li Chu	POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture.	ICPADS (2)	2005	DBLP DOI BibTeX RDF	POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
32	Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh	PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
32	Slo-Li Chu	PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture.	ICPADS	2004	DBLP DOI BibTeX RDF	Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE
31	Marco Lanuzza, Martin Margala, Pasquale Corsonello	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.	ISLPED	2005	DBLP DOI BibTeX RDF	reconfigurable computing, datapath, processor-in-memory
30	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
27	Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
26	Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh	Dynamic Co-operative Intelligent Memory.	DELTA	2008	DBLP DOI BibTeX RDF
26	Thomas L. Sterling	Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing.	NPC	2004	DBLP DOI BibTeX RDF
25	Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler	PIM lite: a multithreaded processor-in-memory prototype.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multithreading, VLSI design, processing-in-memory
25	Jung-Yup Kang, Sandeep Gupta 0001, Jean-Luc Gaudiot	Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture.	CSB	2004	DBLP DOI BibTeX RDF	Processor-In-Memory (PIM) Architecture, Sequence Alignment, BLAST
25	Thomas L. Sterling, Hans P. Zima	Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing.	SC	2002	DBLP DOI BibTeX RDF	Petaflops computing, data parallel processing, parallel architectures, Processor-In-Memory, irregular applications
24	Slo-Li Chu	Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture.	EUC	2007	DBLP DOI BibTeX RDF	Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
22	Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin	Helper thread prefetching for loosely-coupled multiprocessor systems.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Nagarajan Venkateswaran, Aditya Krishnan 0002, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan	Memory in processor: a novel design paradigm for supercomputing architectures.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
20	Brandon J. Jasionowski, Michelle K. Lay, Martin Margala	A Processor-In-Memory Architecture for Multimedia Compression.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
20	Hans P. Zima, Thomas L. Sterling	Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays.	ISHPC	2000	DBLP DOI BibTeX RDF
20	Jaejin Lee, Changhee Jung, Daeseob Lim, Yan Solihin	Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
19	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
18	Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng	A multi-streaming SIMD architecture for multimedia applications.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim
17	Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie	Computational RAM: Implementing Processors in Memory.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
16	Jae Chul Cha, Sandeep K. Gupta 0001	Matrix Inversion on a PIM (Processor-in-Memory).	CSSE (3)	2008	DBLP DOI BibTeX RDF
16	Slo-Li Chu, Wen-Chih Ho, Chien-Fang Chen, Kai-Wei Ceng, Ming-Han Liu	Design a Novel Memory Network for Processor-in-Memory Architectures.	SKG	2017	DBLP DOI BibTeX RDF
16	Danijela Efnusheva, Aristotel Tentov	Design of Processor in Memory with RISC-modified Memory-Centric Architecture.	CSOC (2)	2017	DBLP DOI BibTeX RDF
16	Christopher J. Hughes, Sarita V. Adve	Memory-side prefetching for linked data structures for processor-in-memory systems.	J. Parallel Distributed Comput.	2005	DBLP DOI BibTeX RDF
16	Yan Solihin, Jaejin Lee, Josep Torrellas	Adaptively Mapping Code in an Intelligent Memory Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
16	Dennis W. Prather	Three Dimensional VLSI-Scale Interconnects.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
15	Ed T. Upchurch, Thomas L. Sterling, Jay B. Brockman	Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs.	SC	2004	DBLP DOI BibTeX RDF
13	Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou	Design of a novel SIMD architecture by fusing operations and registers.	ICS	2009	DBLP DOI BibTeX RDF	processor-in-memory, mmx, simd, multimedia extensions, pim
13	Sourav Chatterji, Manikandan Narayanan, Jason Duell, Leonid Oliker	Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine.	IPDPS	2003	DBLP DOI BibTeX RDF	multimedia applications, stream processing, QR decomposition, processor-in-memory, vector architecture
13	Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, Rupak Biswas	Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines.	IPDPS	2002	DBLP DOI BibTeX RDF	memory intensive benchmarks, data parallelism, vector processor, Processor-in-Memory, embedded DRAM
13	G. Jack Lipovski, Clement T. Yu	The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval.	MTDT	1999	DBLP DOI BibTeX RDF
12	M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001	FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?	CoRR	2023	DBLP DOI BibTeX RDF
12	M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001	FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?	FPL	2023	DBLP DOI BibTeX RDF
12	Sung-June Byun, Dong-Gyun Kim, Kyung-Do Park, Yeun-Jin Choi, Pervesh Kumar, Imran Ali, Dong-Gyu Kim, June-Mo Yoo, Hyung-Ki Huh, Yeon-Jae Jung, Seok-Kee Kim, YoungGun Pu, Kang-Yoon Lee	A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications.	Sensors	2022	DBLP DOI BibTeX RDF
12	Kyung Do Park, Dong Gyun Kim, YoungGun Pu, Kang-Yoon Lee	10.76 TOPS/W CNN Algorithm Circuit using Processor-In-Memory with 8T-SRAM.	BigComp	2021	DBLP DOI BibTeX RDF
12	Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly	pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning.	IEEE Comput. Archit. Lett.	2020	DBLP DOI BibTeX RDF
12	Dominique Lavenier, Remy Cimadomo, Romaric Jodin	Variant Calling Parallelization on Processor-in-Memory Architecture.	BIBM	2020	DBLP DOI BibTeX RDF
12	Richard Muri, Paul J. Fortier	Embedded Processor-In-Memory Architecture for Accelerating Arithmetic Operations.	HPEC	2019	DBLP DOI BibTeX RDF
12	Duckhwan Kim 0001	Neurocube: Energy-Efficient Programmable Digital Deep Learning Accelerator based on Processor in Memory Platform.		2019	RDF
12	Dominique Lavenier, Jean-François Roy, David Furodet	DNA mapping using Processor-in-Memory architecture.	BIBM	2016	DBLP DOI BibTeX RDF
12	Joshua Schabel, Lee Baker, Sumon Dey, Weifu Li, Paul D. Franzon	Processor-in-memory support for artificial neural networks.	ICRC	2016	DBLP DOI BibTeX RDF
12	Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi	Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS).	NANOARCH	2015	DBLP DOI BibTeX RDF
12	Jed Kao-Tung Chang, Chen Liu 0001, Jean-Luc Gaudiot	Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture.	IPDPS Workshops	2013	DBLP DOI BibTeX RDF
12	Mohammed Sayed, Wael M. Badawy, Graham A. Jullien	Video-Active RAM: A processor-in-memory architecture for video coding applications.	ISCAS	2010	DBLP DOI BibTeX RDF
12	Jung-Yup Kang, Sandeep K. Gupta 0001, Jean-Luc Gaudiot	An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Real-time and embedded systems, Special-Purpose and Application-Based Systems
12	A. I. Eldosuky, H. A. Ali, M. A. Abbas	An Energy-Efficient FlexRAM Processor-In-Memory chip.	Egypt. Comput. Sci. J.	2006	DBLP BibTeX RDF
12	Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee	Improving workload balance and code optimization on processor-in-memory systems.	J. Syst. Softw.	2004	DBLP DOI BibTeX RDF
12	Slo-Li Chu, Tsung-Chuan Huang	SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory.	J. Syst. Archit.	2004	DBLP DOI BibTeX RDF
12	Tsung-Chuan Huang, Slo-Li Chu	A statement based parallelizing framework for processor-in-memory architectures.	Inf. Process. Lett.	2003	DBLP DOI BibTeX RDF
12	Jung-Yup Kang, Sandeep Gupta 0001, Saurabh Shah, Jean-Luc Gaudiot	An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation.	ASAP	2003	DBLP DOI BibTeX RDF
12	Thomas L. Sterling	The Gilgamesh MIND Processor-in-Memory Architecture for Petaflops-Scale Computing.	ISHPC	2002	DBLP DOI BibTeX RDF
12	Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee	Improving Workload Balance and Code Optimization in Processor-in-Memory Systems.	ICPADS	2001	DBLP DOI BibTeX RDF
12	Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge	Optimizing Data Scheduling on Processor-in-Memory Arrays.	IPPS/SPDP	1998	DBLP DOI BibTeX RDF
11	Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood	Poster reception - The structural simulation toolkit: exploring novel architectures.	SC	2006	DBLP DOI BibTeX RDF
11	John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath	Design of a 3-D fully depleted SOI computational RAM.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
4	Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French	A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels.	ISCA	2003	DBLP DOI BibTeX RDF
4	Jinwoo Suh, Dong-In Kang, Stephen P. Crago	Dynamic Power Management of Multiprocessor Systems.	IPDPS	2002	DBLP DOI BibTeX RDF
4	Hans P. Zima, Thomas L. Sterling	Support for Irregular Computations in Massively Parallel PIM Arrays, Using an Object-Based Execution Model.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF