Search results for "Reorder-Buffer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
105	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
85	Miroslav N. Velev	Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer.	DATE	2002	DBLP DOI BibTeX RDF
83	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Reducing reorder buffer complexity through selective operand caching.	ISLPED	2003	DBLP DOI BibTeX RDF	low-complexity datapath, short-lived values, low-power design, reorder buffer
83	Gurhan Kucuk, Dmitry Ponomarev 0001, Kanad Ghose	Low-complexity reorder buffer architecture.	ICS	2002	DBLP DOI BibTeX RDF	low-complexity datapath, low-power design, reorder buffer
68	Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev 0001	Adaptive reorder buffers for SMT processors.	PACT	2006	DBLP DOI BibTeX RDF	simultaneous multithreading, reorder buffer
68	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
68	Srivatsan Srinivasan, Lizy Kurian John	On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors.	ICCD	1999	DBLP DOI BibTeX RDF	hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer
53	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
51	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
48	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Complexity-Effective Reorder Buffer Designs for Superscalar Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
48	Nirav Dave	Designing a reorder buffer in Bluespec.	MEMOCODE	2004	DBLP DOI BibTeX RDF
48	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose	Distributed Reorder Buffer Schemes for Low Power.	ICCD	2003	DBLP DOI BibTeX RDF
48	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Energy-Efficient Design of the Reorder Buffer.	PATMOS	2002	DBLP DOI BibTeX RDF
48	Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas	A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer.	CHARME	1999	DBLP DOI BibTeX RDF
35	Matthias Menge	Superskalare Prozessoren.	Inform. Spektrum	1998	DBLP DOI BibTeX RDF	Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer
35	D. A. Gilbert, Jim D. Garside	A Result Forwarding Mechanism for Asynchronous Pipelined Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	dependency, asynchronous, Exception, reorder buffer
34	Hyuk-Jun Lee, Eui-Young Chung	Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
34	Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte	A Fast Interrupt Handling Scheme for VLIW Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
32	Xin Fu, James Poe, Tao Li, José A. B. Fortes	Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior.	MASCOTS	2006	DBLP DOI BibTeX RDF
32	Aamer Jaleel, Bruce L. Jacob	Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions.	HPCA	2005	DBLP DOI BibTeX RDF
32	Peter G. Sassone, D. Scott Wills	Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication.	MICRO	2004	DBLP DOI BibTeX RDF
32	Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss	Fetch Halting on Critical Load Misses.	ICCD	2004	DBLP DOI BibTeX RDF
32	Zhenmin Li, Yuqing Ma, Gaoming Du, Xiaolei Wang, Yukun Song, Duoli Zhang	RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
32	Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras	Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions.	IEEE Comput. Archit. Lett.	2021	DBLP DOI BibTeX RDF
32	Md. Enamul Haque, S. M. Zobaed, Muhammad Usama Islam, Faaiza Mohammad Areef	Relaxed Reorder Buffer Commit with Batch Context Switch.	ICCA	2020	DBLP DOI BibTeX RDF
32	Zheng Xu, Jacob Abraham	Resilient Reorder Buffer Design for Network-on-Chip.	ISQED	2019	DBLP DOI BibTeX RDF
32	Cunlu Li, Dezun Dong, Zhonghai Lu, Xiangke Liao	RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router.	IEEE Trans. Parallel Distributed Syst.	2018	DBLP DOI BibTeX RDF
32	Cunlu Li, Dezun Dong, Xiangke Liao, Ji Wu 0006, Fei Lei	RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer.	Hot Interconnects	2016	DBLP DOI BibTeX RDF
32	Won-Jong Lee, Youngsam Shin, Seok Joong Hwang, Seok Kang, Jeong-Joon Yoo, Soojung Ryu	Reorder buffer: an energy-efficient multithreading architecture for hardware MIMD ray traversal.	High Performance Graphics	2015	DBLP DOI BibTeX RDF
32	Stefano Di Carlo, Marco Gaudesi, Edgar E. Sánchez, Matteo Sonza Reorda	A Functional Approach for Testing the Reorder Buffer Memory.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
32	Gaoming Du, Miao Li, Zhonghai Lu, Minglun Gao, Chunhua Wang	An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.	NOCS	2014	DBLP DOI BibTeX RDF
32	Min Choi, Jong Hyuk Park, Young-Sik Jeong	Revisiting reorder buffer architecture for next generation high performance computing.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
32	Stefano Di Carlo, Ernesto Sánchez 0001, Matteo Sonza Reorda	On the on-line functional test of the Reorder Buffer memory in superscalar processors.	DDECS	2013	DBLP DOI BibTeX RDF
32	Jose Raul Garcia Ordaz, Marco Antonio Ramírez Salinas, Luis A. Villa Vargas, Herón Molina Lozano, Cuauhtémoc Peredo Macías	A Reorder Buffer Design for High Performance Processors.	Computación y Sistemas	2012	DBLP BibTeX RDF
32	Mathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt	An out-of-order superscalar processor on FPGA: The ReOrder Buffer design.	DATE	2012	DBLP DOI BibTeX RDF
32	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.	PDP	2010	DBLP DOI BibTeX RDF	AXI protocol, Network on Chip, Buffer Management, Network Interface
32	Woo-Cheol Kwon, Sungjoo Yoo, Junhyung Um, Seh-Woong Jeong	In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem.	DATE	2009	DBLP DOI BibTeX RDF
32	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001	Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors.	Euro-Par	2009	DBLP DOI BibTeX RDF
32	Tuhin Subhra Chakraborty, Saswat Chakrabarti	On output reorder buffer design of bit reversed pipelined continuous data FFT architecture.	APCCAS	2008	DBLP DOI BibTeX RDF
32	Nischal M. Piratla, Anura P. Jayasumana, Abhijit A. Bare, Tarun Banka	Reorder buffer-occupancy density and its application for measurement and evaluation of packet reordering.	Comput. Commun.	2007	DBLP DOI BibTeX RDF
32	Eun-Gu Jung, Dong-Soo Har	Asynchronous Reorder Buffer for Asynchronous On-Chip Bus.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
32	Pierguido V. C. Caironi, Lorenzo Mezzalira, Mariagiovanna Sami	Context Reorder Buffer: An Architectural Support for Real-Time Processing on RISC Architectures.	RTS	1996	DBLP DOI BibTeX RDF
28	Weirong Jiang, Viktor K. Prasanna	Parallel IP lookup using multiple SRAM-based pipelines.	IPDPS	2008	DBLP DOI BibTeX RDF
21	Sumeet Kumar, Aneesh Aggarwal	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
21	Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas	Formal Verification of a Complex Pipelined Processor.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	completion functions, formal verification, PVS, processor verification
21	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
16	Amit Golander, Shlomo Weiss	Checkpoint allocation and release.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback
16	Garo Bournoutian, Alex Orailoglu	Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.	CASES	2009	DBLP DOI BibTeX RDF	compiler assisted hardware, pipeline stalls, embedded processors, data cache
16	Chen Liu 0001, Jean-Luc Gaudiot	The Impact of Resource Sharing Control on the Design of Multicore Processors.	ICA3PP	2009	DBLP DOI BibTeX RDF
16	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
16	Jason Loew, Dmitry Ponomarev 0001	Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures.	ICPP	2008	DBLP DOI BibTeX RDF
16	Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata	High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Interconnection, Ethernet, Multipath, PCI-Express
16	Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho	Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.	ARC	2007	DBLP DOI BibTeX RDF	adaptive pipeline, processor, Asynchronous design
16	Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black	Matrix scheduler reloaded.	ISCA	2007	DBLP DOI BibTeX RDF	picker, scheduler, microarchitecture, matrix, wakeup
16	Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose	Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling
16	Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John	Effective management of multiple configurable units using dynamic optimization.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Adaptive computing environment (ACE), dynamic optimization, power dissipation, hotspots
16	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
16	Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja	The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.	ICS	2006	DBLP DOI BibTeX RDF	benchmark drift, compiler drift, microprocessor design
16	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
16	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
16	Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss 0001	A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	instruction queue, reliability, error correcting codes
16	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative execution for hiding memory latency.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
16	Joshua J. Yi, David J. Lilja, Douglas M. Hawkins	Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	simulation output analysis, measurement techniques, Performance analysis and design aids
16	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers
16	Shadi T. Khasawneh, Kanad Ghose	An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers.	PATMOS	2005	DBLP DOI BibTeX RDF
16	Tingting Sha, Milo M. K. Martin, Amir Roth	Scalable Store-Load Forwarding via Store Queue Index Prediction.	MICRO	2005	DBLP DOI BibTeX RDF
16	Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez	Checkpointed Early Load Retirement.	HPCA	2005	DBLP DOI BibTeX RDF
16	Ryuichi Takahashi, Hajime Ohiwa	Legitimate Peripheral Participation on FPGA for Fine-Grain Microprocessor Design Education.	MSE	2005	DBLP DOI BibTeX RDF
16	Chen Liu 0001, Jean-Luc Gaudiot	Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures.	APPT	2005	DBLP DOI BibTeX RDF
16	Peng Zhou, Soner Önder, Steve Carr 0001	Fast branch misprediction recovery in out-of-order superscalar processors.	ICS	2005	DBLP DOI BibTeX RDF	processor state, checkpoint, recovery, branch misprediction
16	Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Isolating Short-Lived Operands for Energy Reduction.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
16	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez	Toward kilo-instruction processors.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors
16	Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin	Tolerating Hard Faults in Microprocessor Array Structures.	DSN	2004	DBLP DOI BibTeX RDF
16	Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi	Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures.	MICRO	2004	DBLP DOI BibTeX RDF
16	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero	Out-of-Order Commit Processors.	HPCA	2004	DBLP DOI BibTeX RDF
16	Enric Morancho, José María Llabería, Àngel Olivé	A Mechanism for Verifying Data Speculation.	Euro-Par	2004	DBLP DOI BibTeX RDF
16	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF
16	Steven E. Raasch, Steven K. Reinhardt	The Impact of Resource Partitioning on SMT Processors.	IEEE PACT	2003	DBLP DOI BibTeX RDF
16	Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Reducing Datapath Energy through the Isolation of Short-Lived Operands.	IEEE PACT	2003	DBLP DOI BibTeX RDF
16	Daniel Ortega, Eduard Ayguadé, Mateo Valero	Dynamic memory instruction bypassing.	ICS	2003	DBLP DOI BibTeX RDF	on-chip memory management, superscalar processors
16	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.	DATE	2002	DBLP DOI BibTeX RDF
16	Timothy Sherwood, Erez Perelman, Brad Calder	Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications.	IEEE PACT	2001	DBLP DOI BibTeX RDF
16	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.	MICRO	2001	DBLP DOI BibTeX RDF	energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling
16	Jim D. Garside, Stephen B. Furber, S.-H. Chung	AMULET3 Revealed.	ASYNC	1999	DBLP DOI BibTeX RDF
16	John Matthews, Byron Cook, John Launchbury	Microprocessor Specification in Hawk.	ICCL	1998	DBLP DOI BibTeX RDF	Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification