Search results for "Resynthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
140	Hai Zhou 0001	Retiming and resynthesis with sweep are complete for sequential transformation.	FMCAD	2009	DBLP DOI BibTeX RDF
132	Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001	FPGA area reduction by multi-output function based sequential resynthesis.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, logic synthesis, SAT, resynthesis
95	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors With Counterexamples and Resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
95	Jie-Hong Roland Jiang, Wei-Lun Hung	Inductive equivalence checking under retiming and resynthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
80	Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
80	Jie-Hong Roland Jiang, Robert K. Brayton	Retiming and Resynthesis: A Complexity Perspective.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
80	Jie-Hong Roland Jiang	On Some Transformation Invariants Under Retiming and Resynthesis.	TACAS	2005	DBLP DOI BibTeX RDF
65	Demetrios Cantzos, Athanasios Mouchtaris, Chris Kyriakakis	Enhanced Multichannel Audio Resynthesis Through Residual Processing and Features Alignment.	ICME	2007	DBLP DOI BibTeX RDF
65	Irith Pomeranz, Sudhakar M. Reddy	Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
65	R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi	Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
58	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors with Counterexamples and Resynthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking
58	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
52	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
50	Martin Heckmann, Claudius Gläser, Miguel Vaz, Tobias Rodemann, Frank Joublin, Christian Goerick	Listen to the parrot: Demonstrating the quality of online pitch and formant extraction via feature-based resynthesis.	IROS	2008	DBLP DOI BibTeX RDF
50	Yu Hu 0002, Zhe Feng 0002, Lei He 0001, Rupak Majumdar	Robust FPGA resynthesis based on fault-tolerant Boolean matching.	ICCAD	2008	DBLP DOI BibTeX RDF
50	Srimat T. Chakradhar, Sujit Dey	Resynthesis and retiming for optimum partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
50	Christopher K. Lennard, A. Richard Newton	On estimation accuracy for guiding low-power resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
50	Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano	Optimization of hierarchical designs using partitioning and resynthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
50	Kaushik De, Prithviraj Banerjee	PREST: a system for logic partitioning and resynthesis for testability.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
45	Athanasios Mouchtaris, Shrikanth S. Narayanan, Chris Kyriakakis	Multichannel audio synthesis by subband-based spectral conversion and parameter adaptation.	IEEE Trans. Speech Audio Process.	2005	DBLP DOI BibTeX RDF
43	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
43	Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.	ASYNC	1997	DBLP DOI BibTeX RDF	combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit
43	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
37	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
37	W. Knox Carey, Daniel B. Chuang, Sheila S. Hemami	Regularity-Preserving Image Interpolation.	ICIP (1)	1997	DBLP DOI BibTeX RDF	regularity-preserving image interpolation, continuous signal, continuous derivatives, instantaneous luminance transitions, oversmoothed edges, wavelet-based interpolation method, wavelet transform coefficients decay, image resynthesis, average PSNR improvement, bicubic techniques, bilinear techniques, algorithm, image processing, natural images
37	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev	Decomposition and technology mapping of speed-independent circuits using Boolean relations.	ICCAD	1997	DBLP DOI BibTeX RDF	Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
37	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
36	Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang	Scalable don't-care-based logic optimization and resynthesis.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, interpolation, windowing, technology mapping, boolean satisfiability, logic optimization
36	Suresh Raman, Mike Lubyanitsky	Cone Resynthesis ECO Methodology for Multi-Million Gate Designs.	VLSI Design	2009	DBLP DOI BibTeX RDF
36	Murtaza Bulut, Sungbok Lee, Shrikanth S. Narayanan	Recognition for synthesis: Automatic parameter selection for resynthesis of emotional speech from neutral speech.	ICASSP	2008	DBLP DOI BibTeX RDF
36	Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes	Enhancing design robustness with reliability-aware resynthesis and logic simulation.	ICCAD	2007	DBLP DOI BibTeX RDF
36	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou	Incremental physical resynthesis for timing optimization.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
36	Tiberiu Chelcea, Steven M. Nowick	Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems.	DAC	2002	DBLP DOI BibTeX RDF
36	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
36	Priyank Kalla, Maciej J. Ciesielski	Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.	DATE	1999	DBLP DOI BibTeX RDF
36	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
36	Subhrajit Bhattacharya, Franc Brglez, Sujit Dey	Transformations and resynthesis for testability of RT-level control-data path specifications.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
36	Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
36	Sujit Dey, Franc Brglez, Gershon Kedem	Corolla Based Circuit Partitioning and Resynthesis.	DAC	1990	DBLP DOI BibTeX RDF
30	Jason Cong, Kirill Minkovich	Improved SAT-based Boolean matching using implicants for LUT-based FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	logic synthesis, SAT, implicant, boolean matching, FPGA lookup table
30	L.-M. Reissell, Dinesh K. Pai	High Resolution Analysis of Impact Sounds and Forces.	WHC	2007	DBLP DOI BibTeX RDF
30	Milenko Drinic, Darko Kirovski	Behavioral synthesis via engineering change.	DAC	2002	DBLP DOI BibTeX RDF	engineering change, scheduling, transformations, register assignment
30	Enrique San Millán, Luis Entrena, José Alberto Espejo	On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.	DSD	2001	DBLP DOI BibTeX RDF
30	Huiqun Liu, Martin D. F. Wong	Network-flow-based multiway partitioning with area and pin constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
30	Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
30	Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton	Multi-level synthesis for safe replaceability.	ICCAD	1994	DBLP DOI BibTeX RDF
22	Dominic Wist, Mark Schäfer, Walter Vogler, Ralf Wollowski	STG Decomposition: Internal Communication for SI Implementability.	ACSD	2010	DBLP DOI BibTeX RDF	CSC, decomposition, STG, resynthesis, speed independent
22	Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung	Matching-based minimum-cost spare cell selection for design changes.	DAC	2009	DBLP DOI BibTeX RDF	spare cells, matching, physical synthesis, resynthesis, ECO
22	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
22	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	FPGA technology mapping: a study of optimality.	DAC	2005	DBLP DOI BibTeX RDF	resynthesis optimization, FPGA, boolean satisfiability, lookup table, cone
22	Stephen A. Edwards	Making cyclic circuits acyclic.	DAC	2003	DBLP DOI BibTeX RDF	acyclic circuits, cyclic circuits, constructiveness, resynthesis
22	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
22	Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija	CMOS Combinational Circuit Sizing by Stage-wise Tapering.	DATE	1998	DBLP DOI BibTeX RDF	tapering, Transistor sizing, resynthesis
22	Irith Pomeranz, Sudhakar M. Reddy	On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis
22	Roman Kuznar, Franc Brglez	PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	optimization, FPGA, partitioning, resynthesis, critical path delay
22	Demetri Terzopoulos, Keith Waters	Analysis and Synthesis of Facial Image Sequences Using Physical and Anatomical Models.	IEEE Trans. Pattern Anal. Mach. Intell.	1993	DBLP DOI BibTeX RDF	expressions resynthesis, facial image sequences, graphics workstation, physics-based synthetic facial tissue, anatomically motivated facial muscle actuators, dynamical facial muscle contractions, expressive human faces, deformable contour models, image sequences, computer animation, facial animation, video sequences, snakes, biomechanics, biomechanics, face model, anatomical models
21	Siang-Yun Lee, Giovanni De Micheli	Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
21	Ünal Ege Gaznepoglu, Nils Peters	Evaluation of the Speech Resynthesis Capabilities of the VoicePrivacy Challenge Baseline B1.	CoRR	2023	DBLP DOI BibTeX RDF
21	Navin Raj Prabhu, Nale Lehmann-Willenbrock, Timo Gerkmann	In-the-wild Speech Emotion Conversion Using Disentangled Self-Supervised Representations and Neural Vocoder-based Resynthesis.	CoRR	2023	DBLP DOI BibTeX RDF
21	Tu Anh Nguyen, Wei-Ning Hsu, Antony D'Avirro, Bowen Shi, Itai Gat, Maryam Fazel-Zarandi, Tal Remez, Jade Copet, Gabriel Synnaeve, Michael Hassid, Felix Kreuk, Yossi Adi, Emmanuel Dupoux	EXPRESSO: A Benchmark and Analysis of Discrete Expressive Speech Resynthesis.	CoRR	2023	DBLP DOI BibTeX RDF
21	Arianne Meijer-van de Griend	Towards a generic compilation approach for quantum circuits through resynthesis.	CoRR	2023	DBLP DOI BibTeX RDF
21	Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini	Resynthesis-based Attacks Against Logic Locking.	CoRR	2023	DBLP DOI BibTeX RDF
21	Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi	ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Regeneration.	CVPR	2023	DBLP DOI BibTeX RDF
21	Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini	Resynthesis-based Attacks Against Logic Locking.	ISQED	2023	DBLP DOI BibTeX RDF
21	Görkem Gök, Özgül Salor, Müslüm Cengiz Taplamacioglu	An Electric Arc Furnace Model Based on Resynthesis Using Frequency Spectrum Distributions of EAF Currents.	IAS	2023	DBLP DOI BibTeX RDF
21	Tianji Liu, Evangeline F. Y. Young	Rethinking AIG Resynthesis in Parallel.	DAC	2023	DBLP DOI BibTeX RDF
21	Federico Simonetta, Federico Avanzini, Stavros Ntalampiras	A perceptual measure for evaluating the resynthesis of automatic music transcriptions.	Multim. Tools Appl.	2022	DBLP DOI BibTeX RDF
21	Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich	SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
21	Federico Simonetta	Music Interpretation Analysis. A Multimodal Approach To Score-Informed Resynthesis of Piano Recordings.	CoRR	2022	DBLP DOI BibTeX RDF
21	Federico Simonetta, Federico Avanzini, Stavros Ntalampiras	A Perceptual Measure for Evaluating the Resynthesis of Automatic Music Transcriptions.	CoRR	2022	DBLP BibTeX RDF
21	Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi	ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Enhancement.	CoRR	2022	DBLP DOI BibTeX RDF
21	Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli	Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.	ASP-DAC	2022	DBLP DOI BibTeX RDF
21	Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux	Speech Resynthesis from Discrete Disentangled Self-Supervised Representations.	CoRR	2021	DBLP BibTeX RDF
21	Siang-Yun Lee, Heinz Riener, Giovanni De Micheli	Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.	DDECS	2021	DBLP DOI BibTeX RDF
21	Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux	Speech Resynthesis from Discrete Disentangled Self-Supervised Representations.	Interspeech	2021	DBLP DOI BibTeX RDF
21	Jitka Kocnová, Zdenek Vasícek	Resynthesis of logic circuits using machine learning and reconvergent paths.	DSD	2021	DBLP DOI BibTeX RDF
21	Milos Ajcevic, Agostino Accardo, Maria Pia Francescato	Modeling of glycogen resynthesis according to insulin concentration: towards a system for prevention of late-onset exercise-induced hypoglycemia in Type 1 diabetes patients.	KES	2021	DBLP DOI BibTeX RDF
21	Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich	Testability-Enhancing Resynthesis of Reconfigurable Scan Networks.	ITC	2021	DBLP DOI BibTeX RDF
21	Wenting Dai, Marius Erdt, Alexei Sourin	Anomaly Detection and Segmentation Based on Defect Repaired Image Resynthesis.	CW	2021	DBLP DOI BibTeX RDF
21	Hao Shi, Wei Dong 0006, Rui Li 0050, Wanwei Liu	Controller Resynthesis for Multirobot System When Changes Happen.	Computer	2020	DBLP DOI BibTeX RDF
21	Jitka Kocnová, Zdenek Vasícek	EA-based resynthesis: an efficient tool for optimization of digital circuits.	Genet. Program. Evolvable Mach.	2020	DBLP DOI BibTeX RDF
21	Jeongwoo Heo, Taewhan Kim	Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization.	ASP-DAC	2020	DBLP DOI BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Speaker Independence of Neural Vocoders and Their Effect on Parametric Resynthesis Speech Enhancement.	ICASSP	2020	DBLP DOI BibTeX RDF
21	Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich	Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks.	ITC	2020	DBLP DOI BibTeX RDF
21	Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman	Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Speaker independence of neural vocoders and their effect on parametric resynthesis speech enhancement.	CoRR	2019	DBLP BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Speech denoising by parametric resynthesis.	CoRR	2019	DBLP BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Parametric Resynthesis with neural vocoders.	CoRR	2019	DBLP BibTeX RDF
21	Krzysztof Lis, Krishna K. Nakka, Pascal Fua, Mathieu Salzmann	Detecting the Unexpected via Image Resynthesis.	CoRR	2019	DBLP BibTeX RDF
21	Krzysztof Lis, Krishna Kanth Nakka, Pascal Fua, Mathieu Salzmann	Detecting the Unexpected via Image Resynthesis.	ICCV	2019	DBLP DOI BibTeX RDF
21	Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman	Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.	DATE	2019	DBLP DOI BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Parametric Resynthesis With Neural Vocoders.	WASPAA	2019	DBLP DOI BibTeX RDF
21	Soumi Maiti, Michael I. Mandel	Speech Denoising by Parametric Resynthesis.	ICASSP	2019	DBLP DOI BibTeX RDF
21	Christopher Beckham, Sina Honari, Vikas Verma, Alex Lamb, Farnoosh Ghadiri, R. Devon Hjelm, Yoshua Bengio, Chris Pal	On Adversarial Mixup Resynthesis.	NeurIPS	2019	DBLP BibTeX RDF
21	Rafael Trapani Possignolo, Jose Renau	SMatch: Structural Matching for Fast Resynthesis in FPGAs.	DAC	2019	DBLP DOI BibTeX RDF
21	Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel	Area Optimization of Timing Resilient Designs Using Resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
21	Soumi Maiti, Joey Ching, Michael I. Mandel	Large Vocabulary Concatenative Resynthesis.	INTERSPEECH	2018	DBLP DOI BibTeX RDF
21	Ali Raza Syed, Viet Anh Trinh, Michael I. Mandel	Concatenative Resynthesis with Improved Training Signals for Speech Enhancement.	INTERSPEECH	2018	DBLP DOI BibTeX RDF
21	Alexander L. Stempkovskiy, Dmitry V. Telpukhov, Vladislav Nadolenko	Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits.	EWDTS	2018	DBLP DOI BibTeX RDF
21	Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli	Improvements to boolean resynthesis.	DATE	2018	DBLP DOI BibTeX RDF