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Found 246 publication records. Showing 246 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 123 | Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002 |
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.  |
ISLPED  |
2010 |
DBLP DOI BibTeX RDF |
STT-RAM, emerging memory, spintronic |
| 97 | Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili |
An energy efficient cache design using spin torque transfer (STT) RAM. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
(STT)RAM, memory technologies, cache design |
| 45 | Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu |
面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM). |
计算机科学 |
2018 |
DBLP BibTeX RDF |
|
| 43 | Hyunwoo Park, Hyun So, Hyukjun Lee |
Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors. |
IEICE Electron. Express |
2018 |
DBLP DOI BibTeX RDF |
|
| 43 | Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 |
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2014 |
DBLP DOI BibTeX RDF |
|
| 43 | Tiefei Zhang, Tianzhou Chen, Jianzhong Wu, Youtian Qu |
A Selective Read-before-Write Scheme for Energy-Aware Spin Torque Transfer RAM (STT-RAM) Cache Design. |
J. Circuits Syst. Comput. |
2013 |
DBLP DOI BibTeX RDF |
|
| 43 | Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 |
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. |
DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 43 | Wei Xu 0021, Hongbin Sun 0001, Xiaobin Wang, Yiran Chen 0001, Tong Zhang 0002 |
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 43 | Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan |
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 43 | Yiran Chen 0001, Xiaobin Wang, Hai Li 0001, Haiwen Xi, Yuan Yan, Wenzhong Zhu |
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 29 | Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman |
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
| 29 | Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman |
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
| 29 | Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería |
Reuse Detector: Improving the Management of STT-RAM SLLCs. |
CoRR |
2024 |
DBLP DOI BibTeX RDF |
|
| 29 | SatyaJaswanth Badri, Mukesh Saini, Neeraj Goel |
Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems. |
Des. Autom. Embed. Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
| 29 | Sheel Sindhu Manohar, Hemangee K. Kapoor |
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
| 29 | Jinzhi Lai, Jueping Cai, Jie Chu |
A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router. |
IEICE Electron. Express |
2023 |
DBLP DOI BibTeX RDF |
|
| 29 | Gwangeun Byeon, Seongwook Kim, Seokin Hong |
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers. |
ISOCC |
2023 |
DBLP DOI BibTeX RDF |
|
| 29 | Saeed Seyedfaraji, Javad Talafy Daryani, Mohamed M. Sabry Aly, Semeen Rehman |
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | An Yang, Yanfeng Jiang |
Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Jen-Wei Hsieh, Yueh-Ting Hou, Tai-Chieh Chang |
Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor |
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. |
ACM Trans. Embed. Comput. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Saeed Seyedfaraji, Javad Talafy, Mohamed M. Sabry, Semeen Rehman |
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Dhruv Gajaria, Tosiron Adegbija |
Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. |
Future Gener. Comput. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Yogesh Kumar, S. Sivakumar, John Jose |
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. |
VLSI-SoC |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija |
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. |
ICCD |
2022 |
DBLP DOI BibTeX RDF |
|
| 29 | Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh |
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. |
IEEE Comput. Archit. Lett. |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Xiaoxiao Liu 0001, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen 0001 |
Exploring Applications of STT-RAM in GPU Architectures. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Sara Choi, Hong Keun Ahn, Byungkyu Song, Seung-Hyuk Kang, Seong-Ook Jung |
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang |
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. |
IEEE Trans. Computers |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Fateme S. Hosseini, Chengmo Yang |
A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Yao-Hung Huang, Jen-Wei Hsieh |
Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache. |
RTCSA |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Sukarn Agarwal, Shounak Chakraborty 0001 |
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. |
ASAP |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor |
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. |
ISQED |
2021 |
DBLP DOI BibTeX RDF |
|
| 29 | Muhammad Avais Qureshi, Jungwoo Park, Soontae Kim |
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei |
Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches. |
IET Comput. Digit. Tech. |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh |
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. |
Comput. Electr. Eng. |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi |
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. |
Microprocess. Microsystems |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Kyle Kuan, Tosiron Adegbija |
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Quan Deng, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang 0002 |
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh |
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
| 29 | Shashank Suman, Hemangee K. Kapoor |
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. |
ISVLSI |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Yun-Fei Liu, Chun-Feng Wu, Hsin-Wen Wei, Wei-Kuan Shih |
Reinforcing the energy efficiency of cyber-physical systems via direct and split cache consolidation on MLC STT-RAM. |
SAC |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Ping Cheng, Jen-Wei Hsieh |
Early eviction and swapping for MLC STT-RAM-based LLC. |
SAC |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran |
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. |
DATE |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Jingjing Fu, Yu Liu |
A Comprehensive Performance Evaluation to GPGPU Applications under STT- RAM based Hybrid Cache Architectures. |
SBESC |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi |
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. |
COOL CHIPS |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Binbin Liu, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001 |
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng |
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. |
ISQED |
2020 |
DBLP DOI BibTeX RDF |
|
| 29 | Mimi Xie, Chen Pan, Youtao Zhang, Jingtong Hu, Yongpan Liu, Chun Jason Xue |
A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices. |
IEEE Micro |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim |
A Restore-Free Mode for MLC STT-RAM Caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Fazal Hameed, Jerónimo Castrillón |
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Fanfan Shen, Yanxiang He, Jun Zhang 0058, Chao Xu |
Periodic learning-based region selection for energy-efficient MLC STT-RAM cache. |
J. Supercomput. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei |
Energy minimization in the STT-RAM-based high-capacity last-level caches. |
J. Supercomput. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi |
AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches. |
IEEE Trans. Emerg. Top. Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Lei Yang 0018, Weichen Liu, Nan Guan, Nikil D. Dutt |
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router. |
IEEE Trans. Computers |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Kyle Kuan, Tosiron Adegbija |
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. |
IEEE Trans. Computers |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong |
MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. |
ACM Trans. Archit. Code Optim. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu 0002, Jianlei Yang 0001 |
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. |
Sustain. Comput. Informatics Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Keni Qiu, Yujie Zhu, Yuanchao Xu 0002, Qirun Huo, Chun Jason Xue |
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Kyle Kuan, Tosiron Adegbija |
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
| 29 | Kyle Kuan, Tosiron Adegbija |
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
| 29 | Fateme S. Hosseini, Chengmo Yang |
Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM. |
DATE |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-Sun Seo, Bipin Rajendran |
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija |
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. |
IGSC |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Dhruv Gajaria, Tosiron Adegbija |
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Puneet Saraf, Madhu Mutyam |
Endurance enhancement of write-optimized STT-RAM caches. |
MEMSYS |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Pei-Yu Chen, Wei-Kuan Shih |
Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. |
ISLPED |
2019 |
DBLP DOI BibTeX RDF |
|
| 29 | Masayuki Sato 0001, Yoshiki Shoji, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi |
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. |
IEEE Trans. Multi Scale Comput. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Mohammad Taghi Teimoori, Alireza Ejlali |
An Instruction-Level Quality-Aware Method for Exploiting STT-RAM Read Approximation Techniques. |
IEEE Embed. Syst. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | He Zhang 0011, Wang Kang 0001, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao |
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. |
IEEE Access |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Navid Khoshavi, Ronald F. DeMara |
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization. |
IEEE Access |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Jaeyoung Park, Young Uk Yim |
Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM. |
IEEE Trans. Very Large Scale Integr. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón |
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. |
IEEE Trans. Very Large Scale Integr. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei |
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. |
IEEE Trans. Very Large Scale Integr. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Lan Gao, Rui Wang 0014, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai |
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. |
J. Supercomput. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Adnan Nasri, Mahmood Fathy, Ali Broumandnia |
An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads. |
J. Supercomput. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Zihao Liu, Mengjie Mao, Tao Liu 0023, Xue Wang, Wujie Wen, Yiran Chen 0001, Hai Li 0001, Danghui Wang, Yukui Pei, Ning Ge 0001 |
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Bohua Li, Yukui Pei, Wujie Wen |
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM. |
ACM J. Emerg. Technol. Comput. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Yanna Zhu, Danghui Wang |
基于多级磁自旋存储器的Cache调度策略的设计 (Design of Cache Scheduling Policies Based on MLC STT-RAM). |
计算机科学 |
2018 |
DBLP BibTeX RDF |
|
| 29 | Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Behzad Zeinali, Dimitrios Karsinos, Farshad Moradi |
Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería |
Reuse Detector: Improving the Management of STT-RAM SLLCs. |
Comput. J. |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié |
Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM. |
RTNS |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Zihao Liu, Tao Liu 0023, Jie Guo 0002, Nansong Wu, Wujie Wen |
An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Kyle Kuan, Tosiron Adegbija |
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. |
DATE |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi |
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. |
DSD |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Enes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen 0001 |
Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization. |
ASP-DAC |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Bhukya Krishna Priya, Sampath Kumar, B. Shameedha Begum, N. Ramasubramaniam |
Enhancing the lifetime of STT-RAM with MRU replacement algorithm. |
RAIT |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Hengyu Zhao, Jishen Zhao |
Leveraging MLC STT-RAM for energy-efficient CNN training. |
MEMSYS |
2018 |
DBLP DOI BibTeX RDF |
|
| 29 | Sparsh Mittal, Jeffrey S. Vetter, Lei Jiang 0001 |
Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication. |
IEEE Comput. Archit. Lett. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Yuanhui Ni, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu |
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. |
VLSI Design |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001 |
Giant Spin-Hall assisted STT-RAM and logic design. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li |
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Hooman Farkhani, Mohammad Tohidi, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi |
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. |
IEEE Trans. Very Large Scale Integr. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Hyeonggyu Kim, Soontae Kim, Jooheung Lee |
Write-Amount-Aware Management Policies for STT-RAM Caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Lili Song, Ying Wang 0001, Yinhe Han 0001, Huawei Li 0001, Yuanqing Cheng, Xiaowei Li 0001 |
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. |
IEEE Trans. Very Large Scale Integr. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Xunchao Chen, Navid Khoshavi, Ronald F. DeMara, Jun Wang 0001, Dan Huang, Wujie Wen, Yiran Chen 0001 |
Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache. |
IEEE Trans. Computers |
2017 |
DBLP DOI BibTeX RDF |
|
| 29 | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi |
An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors. |
IEEE Trans. Parallel Distributed Syst. |
2017 |
DBLP DOI BibTeX RDF |
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| 29 | Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen 0001 |
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2017 |
DBLP DOI BibTeX RDF |
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| 29 | Sparsh Mittal |
Mitigating Read-disturbance Errors in STT-RAM Caches by Using Data Compression. |
CoRR |
2017 |
DBLP BibTeX RDF |
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