|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 9 occurrences of 8 keywords
|
|
|
|
|
Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 46 | Bhanu Kapoor, V. S. S. Nair |
Improving Path Sensitizability of Combinational Circuits.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
|
| 31 | Ramesh C. Tekumalla, Premachandran R. Menon |
On Redundant Path Delay Faults in Synchronous Sequential Circuits. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults |
| 31 | Ramesh C. Tekumalla |
On Test Set Generation for Efficient Path Delay Fault Diagnosis. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
Sensitizability, test generation, diagnosis, delay faults, robust tests |
| 31 | Ramesh C. Tekumalla, Premachandran R. Menon |
Test generation for primitive path delay faults in combinational circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Sensitizing cubes, static sensitizability, primitive faults, test generation |
| 30 | How-Rern Lin, TingTing Hwang |
On determining sensitization criterion in an iterative gate sizing process. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 30 | Li-Ren Liu, David Hung-Chang Du, Hsi-Chuan Chen |
An efficient parallel critical path algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #6 of 6 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")
data released under the ODC-BY 1.0 license