Search results for "SimICS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
105	Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hållberg, Johan Högberg, Fredrik Larsson, Andreas Moestedt, Bengt Werner	Simics: A Full System Simulation Platform.	Computer	2002	DBLP DOI BibTeX RDF
87	Andrés Ortiz 0001, Julio Ortega Lopera, Antonio F. Díaz, Alberto Prieto	Protocol Offload Evaluation Using Simics.	CLUSTER	2006	DBLP DOI BibTeX RDF
83	Peter S. Magnusson, Bengt Werner	Efficient memory simulation in SimICS.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	efficient memory simulation, SimICS, instruction level simulator, complex memory hierarchies, user level code, system level code, software caching mechanism, Simulator Translation Cache, STC, interpreted memory operations, complex memory simulation code, lazy storage allocation, well defined internal interface, generic memory simulation, user extensions, threaded code, runtime selection, statistics gathering, memory profiling, data structures, data structures, virtual machines, multiprocessors, storage management, storage allocation
69	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
55	Manu Shantharam, Padma Raghavan, Mahmut T. Kandemir	Hybrid Techniques for Fast Multicore Simulation.	Euro-Par	2009	DBLP DOI BibTeX RDF
55	Andrés Ortiz 0001, Julio Ortega Lopera, Antonio F. Díaz, Alberto Prieto	Analyzing the benefits of protocol offload by full-system simulation.	PDP	2007	DBLP DOI BibTeX RDF
36	Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries	A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	resource managment, multicore, control system
36	Lars Albertsson	Holistic Debugging -- Enabling Instruction Set Simulation for Software Quality Assurance.	MASCOTS	2006	DBLP DOI BibTeX RDF
33	Lars Albertsson, Peter S. Magnusson	Using Complete System Simulation for Temporal Debugging of General Purpose Operating Systems and Workload.	MASCOTS	2000	DBLP DOI BibTeX RDF	Temporal Debugging, Simics, Complete System Simulation, Operating Systems, Linux, Soft Real Time Systems
32	Zhenkun Yang, Yuriy Viktorov, Jin Yang 0006, Jiewen Yao, Vincent Zimmer	UEFI Firmware Fuzzing with Simics Virtual Platform.	DAC	2020	DBLP DOI BibTeX RDF
32	Eric Nilsson, Daniel Aarno, Erik Carstensen, Håkan Grahn	Accelerating Graphics in the Simics Full-System Simulator.	MASCOTS	2015	DBLP DOI BibTeX RDF
32	Asad Khan, Weiqiang Ma, Chris Wolf, Bengt Werner	Multi-Threaded Simics SystemC Virtual Platform.	ICCAD	2015	DBLP DOI BibTeX RDF
32	Grigory Rechistov, Arnold Plotkin	Implementation of Intel Restricted Transactional Memory ISA Extension in Simics.	ICCS	2013	DBLP DOI BibTeX RDF
32	Nikrouz Faroughi	Multi-Cache Profiling of Parallel Processing Programs Using Simics.	PDPTA	2006	DBLP BibTeX RDF
32	Nikrouz Faroughi	Profiling of parallel processing programs on shared memory multiprocessors using Simics.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
32	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	Evaluating IA-32 web servers through simics: a practical experience.	J. Syst. Archit.	2005	DBLP DOI BibTeX RDF
32	Jakob Engblom, David Kågedal, Andreas Moestedt, Johan Runeson	Developing embedded networked products using the Simics full-system simulator.	PIMRC	2005	DBLP DOI BibTeX RDF
32	Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenström, Fredrik Lundholm, Magnus Karlsson 0002, Fredrik Dahlgren, Håkan Grahn	SimICS/Sun4m: A Virtual Workstation.	USENIX Annual Technical Conference	1998	DBLP BibTeX RDF
32	Johan Montelius, Peter S. Magnusson	Using SimICS to Evaluate the Penny System.	ILPS	1997	DBLP BibTeX RDF
18	Colin J. Ihrig, Rami G. Melhem, Alex K. Jones	Automated modeling and emulation of interconnect designs for many-core chip multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, interconnection network, emulation, multi-core, many-core
18	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
18	Vikas R. Vasisht, Hsien-Hsin S. Lee	SHARK: Architectural support for autonomic protection against stealth by rootkit exploits.	MICRO	2008	DBLP DOI BibTeX RDF
18	Kyriakos Stavrou, Marios Nikolaides, Demos Pavlou, Samer Arandi, Paraskevas Evripidou, Pedro Trancoso	TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems.	ICPP	2008	DBLP DOI BibTeX RDF
18	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
18	David H. Albonesi	Mixing It Up.	IEEE Micro	2007	DBLP DOI BibTeX RDF	photonic integration, self-reconfigurable hardware, simulation
18	Jianwei Chen, Michel Dubois 0001, Per Stenström	SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators.	IEEE Micro	2007	DBLP DOI BibTeX RDF	simulation, low-power design, power management, modeling of computer architecture
18	Manhee Lee, Minseon Ahn, Eun Jung Kim 0001	I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems.	PACT	2007	DBLP DOI BibTeX RDF
18	Javier Navaridas, Francisco Javier Ridruejo Perez, José Miguel-Alonso	Evaluation of Interconnection Networks Using Full-System Simulators: Lessons Learned.	Annual Simulation Symposium	2007	DBLP DOI BibTeX RDF
18	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
18	Francisco Javier Ridruejo Perez, José Miguel-Alonso, Javier Navaridas	Concepts and components of full-system simulation of distributed memory parallel computers.	HPDC	2007	DBLP DOI BibTeX RDF
18	Ai-Hsin Liu, Robert P. Dick	Automatic run-time extraction of communication graphs from multithreaded applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	communication, benchmarks, synthesis, multithread, task graph, run-time
18	Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood 0001	Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
18	Derek Uluski, Micha Moffie, David R. Kaeli	Characterizing antivirus workload execution.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
18	Youtao Zhang, Lan Gao, Jun Yang 0002, Xiangyu Zhang 0001, Rajiv Gupta 0001	SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors.	HPCA	2005	DBLP DOI BibTeX RDF
18	Francisco Javier Ridruejo Perez, José Miguel-Alonso	INSEE: An Interconnection Network Simulation and Evaluation Environment.	Euro-Par	2005	DBLP DOI BibTeX RDF
18	Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood 0001, Daniel J. Sorin	Simulating a $2M Commercial Server on a $2K PC.	Computer	2003	DBLP DOI BibTeX RDF
18	Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood 0001	Memory System Behavior of Java-Based Middleware.	HPCA	2003	DBLP DOI BibTeX RDF
18	Jianwei Chen, Michel Dubois 0001, Per Stenström	Integrating complete-system and user-level performance/power simulators: the SimWattch approach.	ISPASS	2003	DBLP DOI BibTeX RDF
18	Carl J. Mauer, Mark D. Hill, David A. Wood 0001	Full-system timing-first simulation.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
18	Murali Annavaram, Trung A. Diep, John Paul Shen	Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors.	ICCD	2002	DBLP DOI BibTeX RDF
18	Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood 0001	Timestamp snooping: an approach for extending SMPs.	ASPLOS	2000	DBLP DOI BibTeX RDF