Search results for "TLP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
117	Rocky K. C. Chang, King P. Fung	Transport layer proxy for stateful UDP packet filtering.	ISCC	2002	DBLP DOI BibTeX RDF
117	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
73	Luong Dinh Hung, Shuichi Sakai	Dynamic Estimation of Task Level Parallelism with Operating System Support.	ISPAN	2005	DBLP DOI BibTeX RDF
73	Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho	An Efficient Two-Level Partitioning Algorithm for VLSI Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
68	Joseph J. Sharkey, Dmitry Ponomarev 0001	Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.	ICPP	2006	DBLP DOI BibTeX RDF
59	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
59	Arun Kejariwal, Hideki Saito 0001, Xinmin Tian, Milind Girkar, Wei Li 0015, Utpal Banerjee, Alexandru Nicolau, Constantine D. Polychronopoulos	Lightweight lock-free synchronization methods for multithreading.	ICS	2006	DBLP DOI BibTeX RDF
59	Pen-Chung Yew	Is There Exploitable Thread-Level Parallelism in General-Purpose Application Programs?	IPDPS	2003	DBLP DOI BibTeX RDF
53	Lei Gao, Zhenghu Gong, Yaping Liu, Ming-che Lai, Wei Peng 0005	A TLP approach for BGP based on local speculation.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	local speculation, parallelism, multi-core, BGP
53	Frederic Maris, Pierre Régnier	TLP-GP: Solving Temporally-Expressive Planning Problems.	TIME	2008	DBLP DOI BibTeX RDF
53	Tirath Ramdas, Gregory K. Egan, David Abramson 0001, Kim K. Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
53	Tomasz Madajczak, Henryk Krawczyk	Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.	PARELEC	2006	DBLP DOI BibTeX RDF
51	Anasua Bhowmik, Manoj Franklin	A general compiler framework for speculative multithreading.	SPAA	2002	DBLP DOI BibTeX RDF	TLP compiler, thread formation, parallelization, data dependence, thread-level parallelism (TLP), control dependence, speculative multithreading (SpMT)
47	Sajith Kalathingal	Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture. (Transformer le TLP en DLP avec l'architecture de vectorization dynamique inter-thread).		2016	RDF
47	Frederic Maris	Planification SAT et Planification Temporellement Expressive. Les Systèmes TSP et TLP-GP. (SAT Planning and Temporally Expressive Planning. The TSP and TLP-GP systems).		2009	RDF
47	Sergey Bychikhin, Viktor Dubec, Dionyz Pogany, Erich Gornik, M. Graf, V. Dudek, Winfried Soppa	Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
44	Juan Carlos Saez, Manuel Prieto 0001, Alexandra Fedorova, Sergey Blagodurov	A comprehensive scheduler for asymmetric multicore systems.	EuroSys	2010	DBLP DOI BibTeX RDF	asymmetric multicore, scheduling, operating systems
44	Alexandru Nicolau, Guangqiang Li, Alexander V. Veidenbaum, Arun Kejariwal	Synchronization optimizations for efficient execution on multi-cores.	ICS	2009	DBLP DOI BibTeX RDF	compilers, synchronization, multithreading, code motion
44	Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra	Combining thread level speculation helper threads and runahead execution.	ICS	2009	DBLP DOI BibTeX RDF	multi-cores, thread-level speculation, helper threads, runahead execution
44	Taehwan Choi, Sooel Son, Mohamed G. Gouda, Jorge Arturo Cobb	Pharewell to Phishing.	SSS	2008	DBLP DOI BibTeX RDF
44	Tai-Xiang Lai, Ming-Dou Ker	Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
44	Glória Curilem Saldías, Fernando Mendes de Azevedo, Andréa R. Barbosa	Adaptive Interface Methodology for Intelligent Tutoring Systems.	Intelligent Tutoring Systems	2004	DBLP DOI BibTeX RDF
44	Hai-Feng Guo, Gopal Gupta 0001	A New Mode Declaration for Tabled Predicates.	ICLP	2003	DBLP DOI BibTeX RDF
44	Kenji Watanabe, Wanming Chu, Yamin Li	Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading.	ACSAC	2001	DBLP DOI BibTeX RDF
41	Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	ALP: Efficient support for all levels of parallelism for complex media applications.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	media applications, multimedia, Parallelism, SIMD, vector, TLP, DLP, data-level parallelism
41	Jung Ho Ahn, Mattan Erez, William J. Dally	Tradeoff between data-, instruction-, and thread-level parallelism in stream processors.	ICS	2007	DBLP DOI BibTeX RDF	ILP, TLP, stream processors, aspect ratio, DLP
40	Anasua Bhowmik, Manoj Franklin	Exploiting Data Value Prediction in Compiler Based Thread Formation.	HiPC	2002	DBLP DOI BibTeX RDF	data value prediction, parallelization, profiling, data dependency, thread-level parallelism (TLP), speculative multithreading (SpMT)
38	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic	Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture.	SAMOS	2009	DBLP DOI BibTeX RDF	DTA, many-core architectures
38	Lin Gao 0002, Lian Li 0002, Jingling Xue, Tin-Fook Ngai	Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction.	CC	2009	DBLP DOI BibTeX RDF
38	Frederic Maris, Pierre Régnier	TLP-GP: New Results on Temporally-Expressive Planning Benchmarks.	ICTAI (1)	2008	DBLP DOI BibTeX RDF
38	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu 0001, Changkyu Kim, Jaehyuk Huh 0001, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore	TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	scalable and high-performance computing, Computer architecture, configurable computing
38	Joshua Redstone, Susan J. Eggers, Henry M. Levy	Mini-Threads: Increasing TLP on Small-Scale SMT Processors.	HPCA	2003	DBLP DOI BibTeX RDF
38	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu 0001, Changkyu Kim, Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler, Charles R. Moore	Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture.	ISCA	2003	DBLP DOI BibTeX RDF
29	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
29	Satoshi Amamiya, Makoto Amamiya, Ryuzo Hasegawa, Hiroshi Fujita 0002	A continuation-based noninterruptible multithreading processor architecture.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Parallel processing, Multithreading, Processor architecture, Thread level parallelism, Multithreaded programming
29	Alexandru Nicolau, Guangqiang Li, Arun Kejariwal	Techniques for efficient placement of synchronization primitives.	PPoPP	2009	DBLP DOI BibTeX RDF	performance, parallelization, compilers, multithreading
29	Carlos Madriles, Pedro López 0001, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González 0001	Boosting single-thread performance in multi-core systems through fine-grain multi-threading.	ISCA	2009	DBLP DOI BibTeX RDF	core-fusion, single-thread performance, multicore, automatic parallelization, thread-level parallelism, speculative multithreading
29	Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris	Exploring the performance limits of simultaneous multithreading for memory intensive applications.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Speculative precomputation, Performance analysis, Instruction-level parallelism, Thread-level parallelism, Simultaneous multithreading, Software prefetching
29	Lei Gao, Ming-che Lai, Zhenghu Gong	Exploiting the Thread-Level Parallelism for BGP on Multi-core.	CNSR	2008	DBLP DOI BibTeX RDF	parallelism, multi-core, BGP
29	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
29	Satoshi Amamiya, Masaaki Izumi, Takanori Matsuzaki, Ryuzo Hasegawa, Makoto Amamiya	Fuce: the continuation-based multithreading processor.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	continuation-based multithread programming, multithreading, thread-level parallelism, chip multi-processor
29	Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois 0001, Per Stenström	Loop-level Speculative Parallelism in Embedded Applications.	ICPP	2007	DBLP DOI BibTeX RDF
29	Carlos F. Daganzo, Karen R. Smilowitz	A note on asymptotic formulae for one-dimensional network flow problems.	Ann. Oper. Res.	2006	DBLP DOI BibTeX RDF	Transportation problem, Distance approximations
29	Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris	Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance.	HPCC	2006	DBLP DOI BibTeX RDF
29	Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris	Exploring the Performance Limits of Simultaneous Multithreading for Scientific Codes.	ICPP	2006	DBLP DOI BibTeX RDF
29	James Laudon	Performance/Watt: the new server focus.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
29	Lawrence Spracklen, Santosh G. Abraham	Chip Multithreading: Opportunities and Challenges.	HPCA	2005	DBLP DOI BibTeX RDF
29	Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood 0001	Exploring Processor Design Options for Java-Based Middleware.	ICPP	2005	DBLP DOI BibTeX RDF	Java, Middleware, CMP, workloads, ILP, Characterization
29	Jianzhuang Lu, Chunyuan Zhang, Zhiying Wang, Yun Cheng, Dan Wu	A Case of SCMP with TLS.	ISPA	2004	DBLP DOI BibTeX RDF
29	Kemathat Vibhatavanij, Nian-Feng Tzeng, Angkul Kongmunvattana	Simultaneous Multithreading-Based Routers.	ICPP	2000	DBLP DOI BibTeX RDF
29	Georges Gonthier	Verifying the Safety of a Practical Concurrent Garbage Collector.	CAV	1996	DBLP DOI BibTeX RDF
29	Robert P. Kurshan, Leslie Lamport	Verification of a Multiplier: 64 Bits and Beyond.	CAV	1993	DBLP DOI BibTeX RDF
27	Nadathur Satish, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, Daehyun Kim 0001, Pradeep Dubey	Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	merge network, tlp, performance, databases, sorting, buffer, merge, many-core, simd, radix
27	Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August	Parallel-stage decoupled software pipelining.	CGO	2008	DBLP DOI BibTeX RDF	doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism
26	Anasua Bhowmik, Manoj Franklin	A fast approximate interprocedural analysis for speculative multithreading compilers.	ICS	2003	DBLP DOI BibTeX RDF	pointer analysis, thread-level parallelism (TLP), interprocedural analysis, speculative multithreading (SpMT)
26	Makoto Matsumoto, Yoshiharu Kurita	Twisted GFSR Generators.	ACM Trans. Model. Comput. Simul.	1992	DBLP DOI BibTeX RDF	GF(2m/italic>), TLP-sequences, generalized feedback shift registers, matrix linear congruential generators, m-sequences
24	Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros 0001, Manuel E. Acacio	On the interactions between ILP and TLP with hardware transactional memory.	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
24	Chao-Yang Ke, Yu-Chia Tsui, Bing-Yue Tsui, Ming-Dou Ker	Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods.	IRPS	2023	DBLP DOI BibTeX RDF
24	Harsha B. Variar, Satendra Kumar Gautam, Ashita Kumar, K. M. Amogh, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy, Mayank Shrivastava	Engineering Custom TLP I-V Characteristic Using a SCR-Diode Series ESD Protection Concept.	IRPS	2023	DBLP DOI BibTeX RDF
24	Yi Zhai, Yu Zhang 0086, Shuo Liu, Xiaomeng Chu, Jie Peng, Jianmin Ji, Yanyong Zhang	TLP: A Deep Learning-Based Cost Model for Tensor Program Tuning.	ASPLOS (2)	2023	DBLP DOI BibTeX RDF
24	Yi-Fan Zhang, Lei Sun, Qiang Cao 0001	TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis.	J. Comput. Sci. Technol.	2022	DBLP DOI BibTeX RDF
24	Jingyi Wu, Yang Yu 0051, Siyuan Cheng 0011, Zhenmian Li, Jianxing Yu	Probabilistic multilevel robustness assessment framework for a TLP under mooring failure considering uncertainties.	Reliab. Eng. Syst. Saf.	2022	DBLP DOI BibTeX RDF
24	Shabnam Mahjoub, Mehdi Golsorkhtabaramiri, Seyed Sadegh Salehi Amiri	TLP: Towards three-level loop parallelisation.	IET Comput. Digit. Tech.	2022	DBLP DOI BibTeX RDF
24	Yi Zhai, Yu Zhang 0086, Shuo Liu, Xiaomeng Chu, Jie Peng, Jianmin Ji, Yanyong Zhang	TLP: A Deep Learning-based Cost Model for Tensor Program Tuning.	CoRR	2022	DBLP DOI BibTeX RDF
24	Yuhang Zhu, Shuxin Liu, Yingle Li, Haitao Li	TLP-CCC: Temporal Link Prediction Based on Collective Community and Centrality Feature Fusion.	Entropy	2022	DBLP DOI BibTeX RDF
24	Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros 0001, Manuel E. Acacio	Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.	PDP	2022	DBLP DOI BibTeX RDF
24	Yuchung Cheng, Neal Cardwell, Nandita Dukkipati, Priyaranjan Jha	The RACK-TLP Loss Detection Algorithm for TCP.	RFC	2021	DBLP DOI BibTeX RDF
24	Kathleen Muhonen, Evan Grund, Robert Ashton	High-Speed TLP and ESD Characterization of ICs.	BCICTS	2021	DBLP DOI BibTeX RDF
24	Carlos Bernal, Manuel Jiménez, Fabio Andrade 0001	TLP Generator Setup for Reliable Switching Characterization of Commercial GaN HEMTs.	LATS	2021	DBLP DOI BibTeX RDF
24	Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen	The Correlations between ESD and TLP in Large Array Devices.	ICCE-TW	2020	DBLP DOI BibTeX RDF
24	Wen Yang, Nicholas Stoll, Jiann-Shiun Yuan	ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests.	IRPS	2020	DBLP DOI BibTeX RDF
24	Thiarles S. Medeiros, Janaina Schwarzrock, Antoni C. Navarro, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon	An Application-Driven Approach to Mitigate Aging by Tuning the TLP and Allocation Strategies.	HPCC/DSS/SmartCity	2020	DBLP DOI BibTeX RDF
24	Xiaoxia Liu, Daojing He, Yun Gao, Sencun Zhu, Sammy Chan	TLP-IDS: A Two-layer Intrusion Detection System for Integrated Electronic Systems.	SRDS	2020	DBLP DOI BibTeX RDF
24	Xia Zhao 0004, Zhiying Wang 0003, Lieven Eeckhout	HeteroCore GPU to Exploit TLP-Resource Diversity.	IEEE Trans. Parallel Distributed Syst.	2019	DBLP DOI BibTeX RDF
24	Jun Zhang 0058, Yanxiang He, Fanfan Shen, Qing'an Li, Hai Tan	Memory-aware TLP throttling and cache bypassing for GPUs.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
24	Yawei Cai, Hui Zhao, Mudong Li, Hanqiao Huang	3D real-time path planning based on cognitive behavior optimization algorithm for UAV with TLP model.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
24	Yongseung Yu, Seokwon Kang, Yongjun Park 0001	A compiler-based approach for GPGPU performance calibration using TLP modulation (WIP paper).	LCTES	2019	DBLP DOI BibTeX RDF
24	Patrick Scharf, Christoph Sohrmann, Steffen Holland, Volkhard Beyer	Investigations on current filamentation in PIN diodes using TLP measurements and TCAD simulations.	ESSDERC	2019	DBLP DOI BibTeX RDF
24	Geert Hellings, Philippe Roussel, Nian Wang, Roman Boschke, Shih-Hung Chen, Marko Simicic, Mirko Scholz, Soeren Stoedel, Kris Myny, Dimitri Linten, Paul Hellings, Nowab Reza M. D. Ashif	Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLP.	IRPS	2019	DBLP DOI BibTeX RDF
24	Po-Lin Lin, Shen-Li Chen, Pei-Lin Wu, Yu-Lin Jhou, Sheng-Kai Fan	Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System.	GCCE	2019	DBLP DOI BibTeX RDF
24	Zhen Lin, Michael Mantor, Huiyang Zhou	GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
24	Huakai Shao, Aiping Wu, Yudian Bao, Yue Zhao, Guisheng Zou, Lei Liu	Thermal reliability investigation of Ag-Sn TLP bonds for high-temperature power electronics application.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
24	Qiang Guo, Siyu Sun, Zhihao Zhang, Hongtao Chen, Mingyu Li	Microstructure evolution and mechanical strength evaluation in Ag/Sn/Cu TLP bonding interconnection during aging test.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
24	Tommaso Cilento, Chan-Su Yun, Arsen Terterian, Chang Hwi Lee, Jung Eon Moon, Si Woo Lee, Hyoungcheol Kwon, Manho Seung, Seokkiu Lee	Investigation of layout effects in diode-triggered SCRs under very-fast TLP stress through full-size, calibrated 3D TCAD simulation.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
24	Marco Buonomo, Lorenzo Torto, Marco Barbato, Nicola Wrachien, Antonio Rizzo, Suren A. Gevorgyan, Frederik C. Krebs, Andrea Cester	Analysis of the effects of voltage pulses on P3HT: PCBM polymeric solar cells by means of TLP technique.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
24	Charles Cardoso De Oliveira, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck	Automatic Tuning TLP and DVFS for EDP with a Non-intrusive Genetic Algorithm Framework.	SBESC	2018	DBLP DOI BibTeX RDF
24	Mouna Mahane, David Trémouilles, Marise Bafleur, Benjamin Thon, Marianne Diatta, Lionel Jaouen	New triggering-speed-characterization method for diode-triggered SCR using TLP.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
24	Dennis Helmut, Gerhard K. M. Wachutka, Gerhard Groos	Transient analysis of latent damage formation in SMD capacitors by Transmission Line Pulsing (TLP).	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
24	Yize Wang, Yuan Wang 0001, Guangyi Lu, Jian Cao 0002, Xing Zhang 0002	A novel TLP-based method to deliver IEC 61000-4-2 ESD stress.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
24	Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Stephan Wong	Exploring ILP and TLP on a Polymorphic VLIW Processor.	ARCS	2017	DBLP DOI BibTeX RDF
24	Qi Chen 0008, Cheng Li, Fei Lu 0004, Chenkun Wang, Feilong Zhang 0001, Albert Z. Wang, Jimmy Ng, Ya-Hong Xie	TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection.	NEMS	2017	DBLP DOI BibTeX RDF
24	Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec	Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP.	SBAC-PAD	2016	DBLP DOI BibTeX RDF
24	Matteo Rigato, Clément Fleury, Michael Heer, Mattia Capriotti, Werner Simbürger, Dionyz Pogany	ESD characterization of multi-finger RF nMOSFET transistors by TLP and transient interferometric mapping technique.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
24	Tudor Chirila, Winfried Kaindl, Tobias Reimann, Michael Rüb, Uwe Wahl	Analysis of the role of the parasitic BJT of Super-Junction power MOSFET under TLP stress.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
24	Wei Zhang 0117, Qi Chen 0008, Ming Xia, Rui Ma 0003, Fei Lu 0004, Chenkun Wang, Albert Z. Wang, Ya-Hong Xie	TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs.	ASICON	2015	DBLP DOI BibTeX RDF
24	Heba Khdr, Santiago Pagani, Muhammad Shafique 0001, Jörg Henkel	Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips.	DAC	2015	DBLP DOI BibTeX RDF
24	Ehsan Fatehi, Paul Gratz	ILP and TLP in shared memory applications: a limit study.	PACT	2014	DBLP DOI BibTeX RDF
24	C. Y. Chen	NN-based fuzzy control for TLP systems: A case study of practical structural parameters and wave properties.	Appl. Soft Comput.	2013	DBLP DOI BibTeX RDF
24	Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation.	DATE	2013	DBLP DOI BibTeX RDF
24	Guido Notermans, Sergey Bychikhin, Dionyz Pogany, David Johnsson, Dejan M. Maksimovic	HMM-TLP correlation for system-efficient ESD design.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF