Search results for "Test-per-scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
111	Xiaodong Zhang 0010, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST.	IOLTW	2000	DBLP DOI BibTeX RDF	Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
84	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
83	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
74	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
72	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
68	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.	IOLTS	2006	DBLP DOI BibTeX RDF	Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
67	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
65	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
65	Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu	Scan-Based BIST Using an Improved Scan Forest Architecture.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
59	Nitin Parimi, Xiaoling Sun	Toggle-Masking for Test-per-Scan VLSI Circuits.	DFT	2004	DBLP DOI BibTeX RDF
46	Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem	SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST.	IDT	2015	DBLP DOI BibTeX RDF
45	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
43	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain.	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
37	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
36	Malav Shah, Dipankar Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
35	Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff	A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture.	IEEE Access	2021	DBLP DOI BibTeX RDF
35	Shaochong Lei, Zhen Wang, Zeye Liu 0002, Feng Liang	A unified solution to reduce test power and test volume for Test-per-scan schemes.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
31	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
31	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS (5)	2003	DBLP DOI BibTeX RDF
29	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
26	Zhiyuan He 0002, Gert Jervan, Zebo Peng, Petru Eles	Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.	DSD	2005	DBLP DOI BibTeX RDF
26	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Power profile manipulation: a new approach for reducing test application time under power constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
25	P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos	Accumulator based Test-per-Scan BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
25	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.	ITC	1999	DBLP DOI BibTeX RDF
24	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
18	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	A Technique to Reduce Power and Test Application Time in BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Snehal Udar, Dimitri Kagaris	LFSR Reseeding with Irreducible Polynomials.	IOLTS	2007	DBLP DOI BibTeX RDF