Search results for "UCLID"

Found 15 publication records. Showing 15 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant	Modeling and Verification of Out-of-Order Microprocessors in UCLID.	FMCAD	2002	DBLP DOI BibTeX RDF
102	Zaher S. Andraus, Karem A. Sakallah	Automatic abstraction and verification of verilog models.	DAC	2004	DBLP DOI BibTeX RDF	UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog
87	Panagiotis Manolios, Sudarshan K. Srinivasan	A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.	J. Autom. Reason.	2006	DBLP DOI BibTeX RDF	pipelined machines, bit-level, verification, refinement, automated reasoning, ACL2
80	Randal E. Bryant	System modeling and verification with UCLID.	MEMOCODE	2004	DBLP DOI BibTeX RDF
65	Randal E. Bryant	Formal Verification of Infinite State Systems Using Boolean Methods.	LICS	2006	DBLP DOI BibTeX RDF
58	Shuvendu K. Lahiri, Sanjit A. Seshia	The UCLID Decision Procedure.	CAV	2004	DBLP DOI BibTeX RDF
44	Panagiotis Manolios, Sudarshan K. Srinivasan	A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.	CHARME	2005	DBLP DOI BibTeX RDF
36	Benoît Guillard, Edoardo Remelli, Pascal Fua	UCLID-Net: Single View Reconstruction in Object Space.	CoRR	2020	DBLP BibTeX RDF
36	Benoît Guillard, Edoardo Remelli, Pascal Fua	UCLID-Net: Single View Reconstruction in Object Space.	NeurIPS	2020	DBLP BibTeX RDF
36	Simon Schwan, Paula Herber	Optimized Hardware/Software Co-Verification using the UCLID Satisfiability Modulo Theory Solver.	WETICE	2020	DBLP DOI BibTeX RDF
22	Panagiotis Manolios, Sudarshan K. Srinivasan	Automatic verification of safety and liveness for pipelined machines using WEB refinement.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	flushing, pipelined machines, verification, refinement, SAT, bisimulation, commitment, liveness, Refinement maps
22	Orly Meir, Ofer Strichman	Yet Another Decision Procedure for Equality Logic.	CAV	2005	DBLP DOI BibTeX RDF
22	Panagiotis Manolios, Sudarshan K. Srinivasan	Refinement Maps for Efficient Verification of Processor Models.	DATE	2005	DBLP DOI BibTeX RDF
22	Randal E. Bryant, Sanjit A. Seshia	Decision Procedures Customized for Formal Verification.	CADE	2005	DBLP DOI BibTeX RDF
22	Panagiotis Manolios, Sudarshan K. Srinivasan	Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements.	DATE	2004	DBLP DOI BibTeX RDF