Search results for "Variation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
61	Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001	Test structures for delay variability.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
59	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	ISLPED	2005	DBLP DOI BibTeX RDF	Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt
55	Jos J. Mellema, Wouter H. Mallee, Thierry G. Guitton, C. Niek van Dijk, David Ring, Job N. Doornberg, Science of Variation Group, Traumaplatform Study Collaborative	Online Studies on Variation in Orthopedic Surgery: Computed Tomography in MPEG4 Versus DICOM Format.	J. Digit. Imaging	2017	DBLP DOI BibTeX RDF
50	Lerong Cheng, Puneet Gupta 0001, Costas J. Spanos, Kun Qian 0014, Lei He 0001	Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.	DAC	2009	DBLP DOI BibTeX RDF	leakage analysis, process variaion, timing, SSTA
49	Georgios Karakonstantis, Kaushik Roy 0001	Low-Power and Variation-Tolerant Application-Specific System Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
49	Swaroop Ghosh	Effect of Variations and Variation Tolerance in Logic Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
49	Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon	Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
49	Nikil Mehta, André DeHon	Variation and Aging Tolerance in FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
49	Hamid Mahmoodi	Low-Power and Variation-Tolerant Memory Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
49	Meeta Sharma Gupta, Pradip Bose	Variation-Tolerant Microprocessor Architecture at Low Power.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
47	Tahir Nawaz Minhas, Markus Fiedler, Patrik Arlos	Quantification of packet delay variation through the coefficient of throughput variation.	IWCMC	2010	DBLP DOI BibTeX RDF	coefficient of throughput variation, network measurement traffice shapping, packet delay variation, traffic shaper, performance analysis, throughput
47	J. Brian Burns, Richard S. Weiss, Edward M. Riseman	View Variation of Point-Set and Line-Segment Features.	IEEE Trans. Pattern Anal. Mach. Intell.	1993	DBLP DOI BibTeX RDF	feature variation, view variation, 3D point sets, weak perspective approximation, 2D line segment features, feature extraction, image recognition, image recognition
47	Peng Xu, Timothy Kennell Jr., Min Gao, Human Genome Structural Variation Consortium, Robert P. Kimberly, Zechen Chong	MRLR: unraveling high-resolution meiotic recombination by linked reads.	Bioinform.	2020	DBLP DOI BibTeX RDF
47	Takeo Kanade, Masatoshi Okutomi	A Stereo Matching Algorithm with an Adaptive Window: Theory and Experiment.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	stereo matching algorithm, reliable matching, projective distortion, maximum correlation, sum of squared differences, disparity distribution, disparity variation, iterative stereo matching algorithm, uncertainty, image sequences, statistical analysis, iterative methods, statistical model, stereo image processing, correlation methods, real images, synthetic images, disparity map, adaptive window, window size, disparity estimate, intensity variation
47	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
43	Glenn Healey, Raghava Kondepudy	Radiometric CCD camera calibration and noise estimation.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	semiconductor device noise, radiometric CCD camera calibration, primary cue, material reflectance, digitized pixel values, sensor noise, scene variation, camera characterization, fixed pattern nonuniformity, spatial variation, dark current, computer vision, edge detection, edge detection, reflectivity, parameter estimation, calibration, shape from shading, video cameras, video cameras, scene description, visual processes, CCD image sensors, noise estimation, semiconductor device models, radiometry
43	Borislava I. Simidchieva, Leon J. Osterweil	Categorizing and modeling variation in families of systems: a position paper.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	software families, software product lines, system architectures, variability, variation
43	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
42	Liang-Jie Zhang, Ali Arsanjani, Abdul Allam, Dingding Lu, Yi-Min Chee	Variation-Oriented Analysis for SOA Solution Design.	IEEE SCC	2007	DBLP DOI BibTeX RDF
42	Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki	Approach for physical design in sub-100 nm era.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
41	Sachin S. Sapatnekar	Statistical Design of Integrated Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
41	Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee	Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
41	Wei Zhang 0012, James Williamson, Li Shang	Power Dissipation.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
41	Aditya Bansal, Rahul M. Rao	Variations: Sources and Characterization.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
41	Nikil Mehta, André DeHon	Low-Power Techniques for FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
41	Bipul C. Paul, Arijit Raychowdhury	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
39	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
39	Rich Hilliard	On representing variation.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	features, variation, architecture description, concerns
39	Lin Huang 0002, Qiang Xu 0001	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
39	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa	Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
39	Jae-Seok Yang, Andrew R. Neureuther	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.	ISQED	2008	DBLP DOI BibTeX RDF	worst corner, noise, crosstalk, variation, signal integrity
39	Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.	DAC	2008	DBLP DOI BibTeX RDF	atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation
39	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
39	Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu	Re-synthesis for delay variation tolerance.	DAC	2004	DBLP DOI BibTeX RDF	tolerance, delay variation
39	Hyung-Soo Lee, Daijin Kim 0001	Tensor-Based AAM with Continuous Variation Estimation: Application to Variation-Robust Face Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	2009	DBLP DOI BibTeX RDF
39	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
39	Nanjangud C. Narendra, Karthikeyan Ponnalagu	Variation-Oriented Requirements Analysis (VORA).	IEEE SCW	2007	DBLP DOI BibTeX RDF
38	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
35	Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar	Circuit techniques for dynamic variation tolerance.	DAC	2009	DBLP DOI BibTeX RDF	dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
35	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
35	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
35	Jason Cong, Albert Liu, Bin Liu 0006	A variation-tolerant scheduler for better than worst-case behavioral synthesis.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, variation, behavioral synthesis
35	Aarti Choudhary, Sandip Kundu	A process variation tolerant self-compensating FinFET based sense amplifier design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sense amplifier, robustness, process -variation, yield, sram, finfet
35	Andreas Lanitis, Christopher J. Taylor 0001	Towards Automatic Face Identification Robust to Ageing Variation.	FG	2000	DBLP DOI BibTeX RDF	Ageing Variation, Face Recognition
35	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
35	Jae-Seok Yang, David Z. Pan	Overlay aware interconnect and timing variation modeling for double patterning technology.	ICCAD	2008	DBLP DOI BibTeX RDF
35	Martin Hansson, Atila Alvandpour	Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Marvin Tom, David Leong, Guy G. Lemieux	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
35	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
35	Jay Ramanathan	Fractal architecture for the adaptive complex enterprise.	Commun. ACM	2005	DBLP DOI BibTeX RDF
31	Wangyang Zhang, Xin Li 0001, Rob A. Rutenbar	Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference.	DAC	2010	DBLP DOI BibTeX RDF	variation characterization, process variation, integrated circuit
31	Kanak Agarwal	On-die sensors for measuring process and environmental variations in integrated circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	environmental variation, test structure, monitors, sensors, process variation, characterization
31	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
31	Maria Teresa Andrade, Artur Pimenta Alves	Experiments with Dynamic Multiplexing and UPC Renegotiation for Video over ATM.	NETWORKING	2000	DBLP DOI BibTeX RDF	renegotiation Abbreviations: AAL, ATM Adaptation Layer, ACTS, Advanced Communications, Technologies & Services, CDV, Cell Delay Variation, CDVT, Cell Delay Variation Tolerance, CTD, Cell Transfer Delay, EFCI, Explicit Forward Congestion Indication, GOP, Group Of Pictures, MBS, Maximum Burst Size, Motion Picture Expert Group, Network Interface Card, Peak Cell Rate, MCR, Minimum Cell Rate, Resource and Management, Sustainable Cell Rate, UNI, User Network Interface, Usage Parameter Control, Quality of Service, QoS, Quality of Service, ATM, ATM, Asynchronous Transfer Mode, VoD, Video on Demand, CAC, MPEG, CBR, statistical multiplexing, VBR, Variable Bit Rate, Connection Admission Control, UPC, UPC, ABR, Virtual Circuit, RM, Available Bit Rate, SCR, PCR, VC, NIC, Constant Bit Rate
31	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
31	Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph	Process variation characterization of chip-level multiprocessors.	DAC	2009	DBLP DOI BibTeX RDF	software, process variation, characterization
31	Seyed-Abdollah Aftabjahani, Linda S. Milor	Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis
31	Pi-Rong Sheu, Shan-Tai Chen	On the Hardness of Approximating the Multicast Delay Variation Problem.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	inter-destination delay variation, NP-complete, NP-hard, multicast routing, Inapproximability
31	Yan Lin 0001, Lei He 0001	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, uncertainty, process variation, stochastic, physical synthesis
31	Louis Scheffer	An overview of on-chip interconnect variation.	SLIP	2006	DBLP DOI BibTeX RDF	causes of variability, on-chip variation, design rules
31	Charles C. Chiang, Jamil Kawa	Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation.	APCCAS	2006	DBLP DOI BibTeX RDF
31	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
31	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.	DAC	2005	DBLP DOI BibTeX RDF	ACLV, layout, manufacturability, compensation, variation, focus
31	Andreas Lanitis, Christopher J. Taylor 0001, Timothy F. Cootes	Toward Automatic Simulation of Aging Effects on Face Images.	IEEE Trans. Pattern Anal. Mach. Intell.	2002	DBLP DOI BibTeX RDF	aging variation, statistical face models, face recognition
31	Kanakagiri Raghavendra, Madhu Mutyam	Process Variation Aware Issue Queue Design.	DATE	2008	DBLP DOI BibTeX RDF
31	Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari 0002, Josep Torrellas	EVAL: Utilizing processors with variation-induced timing errors.	MICRO	2008	DBLP DOI BibTeX RDF
31	Yanming Jia, Yici Cai, Xianlong Hong	Full-chip routing system for reducing Cu CMP & ECP variation.	SBCCI	2008	DBLP DOI BibTeX RDF	electroplating, routing, chemical mechanical polishing
31	Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan	Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.	ISQED	2007	DBLP DOI BibTeX RDF
31	Zhuo Li 0001, Xiang Lu, Weiping Shi	Process variation dimension reduction based on SVD.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
31	Takao Yamashita	Dynamic Replica Control Based on Fairly Assigned Variation of Data with Weak Consistency for Loosely Coupled Distributed Systems.	ICDCS	2002	DBLP DOI BibTeX RDF
31	Jussi Karlgren, Troy Straszheim	Visualizing Stylistic Variation.	HICSS (6)	1997	DBLP DOI BibTeX RDF
31	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Wenjian Yu, Chao Hu, Wangyang Zhang	Variational capacitance extraction of on-chip interconnects based on continuous surface model.	DAC	2009	DBLP DOI BibTeX RDF	geometric variation modeling, hermite polynomial chaos method, quadratic variation model, variational capacitance extraction, spatial correlation
27	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
27	Edson J. R. Justino, Abdenaim El Yacoubi, Flávio Bortolozzi, Robert Sabourin	An Off-Line Signature Verification System using Hidden Markov Model and Cross-Validation.	SIBGRAPI	2000	DBLP DOI BibTeX RDF	off-line signature verification system, pre-processing process, segmentation process, feature extraction process, random falsifications, false acceptance concept, false rejection concept, intrapersonal variation, interpersonal variation, automatic decision threshold derivation, hidden Markov model, handwriting recognition, cross-validation, learning process
27	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
27	Mirko Lucchese, N. Alberto Borghese	Denoising of Digital Radiographic Images with Automatic Regularization Based on Total Variation.	ICIAP	2009	DBLP DOI BibTeX RDF	total variation filtering, gradient descent minimization, regularization, Bayesian filtering, Digital radiography
27	Amlan Ghosh, Rahul M. Rao, Richard B. Brown	A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation.	ISLPED	2009	DBLP DOI BibTeX RDF	fine-grain body-biasing, process variation compensation, slewrate
27	Alex Sawatzky, Christoph Brune, Jahn Müller, Martin Burger 0001	Total Variation Processing of Images with Poisson Statistics.	CAIP	2009	DBLP DOI BibTeX RDF	Poisson noise, Regularization techniques, Segmentation, Denoising, Positron emission tomography, Total variation
27	Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik	A parametric approach for handling local variation effects in timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	on chip variation (OCV), timing, parametric analysis
27	David Wolpert 0001, Paul Ampadu	Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates.	NanoNet	2008	DBLP DOI BibTeX RDF	Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate
27	Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz	Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors.	NanoNet	2008	DBLP DOI BibTeX RDF	nanoscale processor, process variation, defect tolerance
27	A. K. M. Khaled Ahsan Talukder, Michael Kirley, Rajkumar Buyya	A pareto following variation operator for fast-converging multiobjective evolutionary algorithms.	GECCO	2008	DBLP DOI BibTeX RDF	variation operator, evolutionary multiobjective optimization, function evaluation, dynamic system identification
27	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
27	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
27	Bin Zhang 0011, Michael Orshansky	Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation.	ISQED	2008	DBLP DOI BibTeX RDF	temperature variation, NBTI
27	Kimmo Kettunen 0001, Eija Airio, Kalervo Järvelin	Restricted inflectional form generation in management of morphological keyword variation.	Inf. Retr.	2007	DBLP DOI BibTeX RDF	Best-match IR, Inflected indexes, Frequent case form generation for keywords, Generative methods in management of keyword variation
27	Shu Xiao 0001, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
27	Heiko Ludwig, Kamal Bhattacharya, Thomas Setzer	A Layered Service Process Model for Managing Variation and Change in Service Provider Operations.	WISE	2007	DBLP DOI BibTeX RDF	Variation Management, Service Transition, Service Workflow Management, Service Process Evolution, Change Management
27	Lv-an Tang, Bin Cui 0001, Hongyan Li 0002, Gaoshan Miao, Dongqing Yang, Xinbiao Zhou	Effective variation management for pseudo periodical streams.	SIGMOD Conference	2007	DBLP DOI BibTeX RDF	date stream, pattern growth, pseudo periodicity, variation management
27	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
27	Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang	Principle hessian direction based parameter reduction for interconnect networks with process variation.	SLIP	2007	DBLP DOI BibTeX RDF	principle Hessian directions, process variation, timing analysis
27	Kimmo Kettunen 0001	Management of keyword variation with frequency based generation of word forms in IR.	SIGIR	2007	DBLP DOI BibTeX RDF	management of morphological variation, monolingual information retrieval, word form generation, evaluation
27	Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
27	Mehrdad Nourani, Arun Radhakrishnan	Testing On-Die Process Variation in Nanometer VLSI.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator
27	James Donald, Margaret Martonosi	Power efficiency for variation-tolerant multicore processors.	ISLPED	2006	DBLP DOI BibTeX RDF	power, multicore, parallel applications, variation
27	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
27	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
27	Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya	Effect of Process Variation on the Performance of Phase Frequency Detector.	DFT	2006	DBLP DOI BibTeX RDF	Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise
27	Guoliang Xu, Qin Zhang 0005	Minimal Mean-Curvature-Variation Surfaces and Their Applications in Surface Modeling.	GMP	2006	DBLP DOI BibTeX RDF	Minimal mean-curvature-variation flow, Discretization, Surface modeling, Energy functional, Euler-Lagrange equation