Search results for "Verilog-HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Soft IP Protection: Watermarking HDL Codes.	Information Hiding	2004	DBLP DOI BibTeX RDF
77	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
75	Arash Saifhashemi, Hossein Pedram	Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.	DAC	2003	DBLP DOI BibTeX RDF	CHP, PLI, CSP, asynchronous circuits, channel, verilog
68	Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang	Hardware/Software Partitioning in Verilog.	ICFEM	2002	DBLP DOI BibTeX RDF
66	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
59	Choudhury A. Rahman, Wael M. Badawy	A quarter pel full search block motion estimation architecture for H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
49	Raik Brinkmann, Rolf Drechsler	RTL-Datapath Verification using Integer Linear Programming.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
49	Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia	The future of system design languages (panel session).	DAC	2000	DBLP DOI BibTeX RDF
40	Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang	A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology.	HIS (1)	2009	DBLP DOI BibTeX RDF	FPGA, algorithm, pipeline, square root, Verilog HDL
40	Yang Zhang, Xiumin Wang, Yuduo Wang	A New Design of HDB3 Encoder and Decoder Based on FPGA.	HIS (1)	2009	DBLP DOI BibTeX RDF	HDB3, FPGA, encoder, decoder, Verilog HDL
40	Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto	System-Level Design of IEEE1394 Bus Segment Bridge.	ISSS	2002	DBLP DOI BibTeX RDF	HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL
40	Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel	ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL
39	Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil	Automatic Constraint Based Test Generation for Behavioral HDL Models.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
39	Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.	IWDC	2004	DBLP DOI BibTeX RDF
39	John A. Nestor	Teaching Computer Organization with HDLs: An Incremental Approach.	MSE	2005	DBLP DOI BibTeX RDF
39	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.	ISPDC	2003	DBLP DOI BibTeX RDF
37	Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman	An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL.	CoRR	2023	DBLP DOI BibTeX RDF
37	Lekshmi S. Ajay, Sreenidhi Prabha Rajeev	Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA.	ICCCNT	2023	DBLP DOI BibTeX RDF
37	Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki	A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
37	K. N. Raja Praveen, Gadug Sudhamsu	Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers.	IC3I	2022	DBLP DOI BibTeX RDF
37	K. N. Raja Praveen, Gadug Sudhamsu	Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers.	IC3I	2022	DBLP DOI BibTeX RDF
37	Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee	Modeling of nano-scale PLL using Verilog HDL.	ICTC	2022	DBLP DOI BibTeX RDF
37	Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su	Implement 32-bit RISC-V Architecture Processor using Verilog HDL.	ISPACS	2021	DBLP DOI BibTeX RDF
37	Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann	Verilog HDL and its ancestors and descendants.	Proc. ACM Program. Lang.	2020	DBLP DOI BibTeX RDF
37	Junya Miura, Hiromu Miyazaki, Kenji Kise	A portable and Linux capable RISC-V computer system in Verilog HDL.	CoRR	2020	DBLP BibTeX RDF
37	Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen	IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL.	SMC	2020	DBLP DOI BibTeX RDF
37	Abdul Rafay Khatri, Ali Hayek, Josef Börcsök	Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool.	DASC/PiCom/DataCom/CyberSciTech	2018	DBLP DOI BibTeX RDF
37	Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin	Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control.	Int. J. Bifurc. Chaos	2017	DBLP DOI BibTeX RDF
37	Bei Cao, Tianliang Xu, Pengfei Wu	RSA Encryption Algorithm Design and Verification Based on Verilog HDL.	MLICOM (1)	2017	DBLP DOI BibTeX RDF
37	Ryohei Kobayashi, Tomohiro Misono, Kenji Kise	A High-speed Verilog HDL Simulation Method using a Lightweight Translator.	SIGARCH Comput. Archit. News	2016	DBLP DOI BibTeX RDF
37	Zbigniew Jaworski	Verilog HDL model based thermometer-to-binary encoder with bubble error correction.	MIXDES	2016	DBLP DOI BibTeX RDF
37	Shinya Takamaeda-Yamazaki	Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.	ARC	2015	DBLP DOI BibTeX RDF
37	Tze Sin Tan, Bakhtiar Affendi Rosdi	Verilog HDL Simulator Technology: A Survey.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
37	Tariq B. Ahmad, Maciej J. Ciesielski	Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning.	ISVLSI	2014	DBLP DOI BibTeX RDF
37	Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes	Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.	UKSim	2010	DBLP DOI BibTeX RDF
37	Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon	Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research.	FCCM	2010	DBLP DOI BibTeX RDF
37	Adam Duley, Chris Spandikow, Miryung Kim	A program differencing algorithm for verilog HDL.	ASE	2010	DBLP DOI BibTeX RDF
37	Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi	FPGA-Based Fault Injection into Synthesizable Verilog HDL Models.	SSIRI	2008	DBLP DOI BibTeX RDF
37	Robert B. Reese, Mitchell A. Thornton	Introduction to Logic Synthesis using Verilog HDL		2006	DOI RDF
37	Mile K. Stojcev	Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
37	Jordan Dimitriov	Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems.		2002	RDF
37	Daniel C. Hyde	Using verilog HDL to teach computer architecture concepts.	WCAE@ISCA	1998	DBLP DOI BibTeX RDF
37	Gordon G. Pace	Hardware design based on Verilog HDL.		1998	RDF
37	Ulrich Golze	VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL.		1995	RDF
37	Michael J. C. Gordon	The Semantic Challenge of Verilog HDL	LICS	1995	DBLP DOI BibTeX RDF
37	Felice Balarin, Gary York	Verilog HDL Modeling Styles for Formal Verification.	CHDL	1993	DBLP BibTeX RDF
29	Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong	C-Based Design Methodology for FPGA Implementation of ClustalW MSA.	PRIB	2007	DBLP DOI BibTeX RDF	ClustalW, FPGA, multiple sequence alignment, sequence analysis
29	Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand	Assessment of Message Missing Failures in FlexRay-Based Networks.	PRDC	2007	DBLP DOI BibTeX RDF
29	Ryuichi Takahashi, Noriyoshi Yoshida	Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1.	MSE	1999	DBLP DOI BibTeX RDF
29	Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin	An efficient H.264 intra frame coder system design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
29	Esra Sahin, Ilker Hamzaoglu	Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm.	DATE	2007	DBLP DOI BibTeX RDF
29	Esra Sahin, Ilker Hamzaoglu	An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding.	DSD	2007	DBLP DOI BibTeX RDF
29	Serkan Oktem, Ilker Hamzaoglu	An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation.	DSD	2007	DBLP DOI BibTeX RDF
29	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf	Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
29	Sinan Yalcin, Ilker Hamzaoglu	A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
29	Mustafa Parlak, Ilker Hamzaoglu	An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter.	AHS	2006	DBLP DOI BibTeX RDF
29	Ivan Blunno, Luciano Lavagno	Designing an Asynchronous Microcontroller Using Pipefitter.	ICCD	2002	DBLP DOI BibTeX RDF
29	Jordan Dimitrov	Operational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
29	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò	Gate-level power and current simulation of CMOS integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
19	Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner	Fpga-based face detection system using Haar classifiers.	FPGA	2009	DBLP DOI BibTeX RDF	haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
19	Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro	Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.	ARC	2009	DBLP DOI BibTeX RDF	Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
19	Chun-Lung Hsu, Yu-Sheng Huang	A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
19	Christian Haufe, Frank Rogin	Ad-Hoc Translations to Close Verilog Semantics Gap.	DDECS	2008	DBLP DOI BibTeX RDF
19	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
19	Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi	Fault Effects in FlexRay-Based Networks with Hybrid Topology.	ARES	2008	DBLP DOI BibTeX RDF	FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation
19	Ruchika Verma, Ali Akoglu	A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation.	IPDPS	2008	DBLP DOI BibTeX RDF
19	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
19	Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito	A Tiny Processing System for Education and Small Embedded Systems on the FPGAs.	EUC (2)	2008	DBLP DOI BibTeX RDF
19	Shahid Rizwan	Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Xiang Xiao, Jaehwan John Lee	A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
19	Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin	A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network
19	Muhammad T. Anan, Ghulam M. Chaudhry	A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches.	ICC	2007	DBLP DOI BibTeX RDF
19	Xiao Hu, Pengyong Ma, Shuming Chen	Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor.	ICESS	2007	DBLP DOI BibTeX RDF
19	Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang	Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol.	FGCN (2)	2007	DBLP DOI BibTeX RDF
19	Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim	Binary-Truncated CDMA-Based On-Chip Network.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong	A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD.	ICEC	2007	DBLP DOI BibTeX RDF	Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur
19	Mustafa Parlak, Ilker Hamzaoglu	A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm.	AHS	2007	DBLP DOI BibTeX RDF
19	Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang	Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm.	ICCSA (1)	2007	DBLP DOI BibTeX RDF	Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag
19	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong	An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	MMM (2)	2007	DBLP DOI BibTeX RDF	VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm
19	Jaehwan John Lee, Vincent John Mooney	A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip
19	Alexander Kamkin	The UniTESK Approach to Specification-Based Validation of Hardware Designs.	ISoLA	2006	DBLP DOI BibTeX RDF
19	Baofeng Li, Qiang Shao	Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000.	CIT	2006	DBLP DOI BibTeX RDF
19	Choudhury A. Rahman, Wael M. Badawy	An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
19	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto	An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	ISVC (2)	2006	DBLP DOI BibTeX RDF
19	Zude Zhou, Songlin Cheng, Quan Liu	Application of DDR Controller for High-speed Data Acquisition Board.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
19	Pawel Garstecki, Adam Luczak, Marta Stepniewska	A bit-serial implementation of mode decision algorithm for AVC encoders.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Kimo Kim, In-Cheol Park	Combined image signal processing for CMOS image sensors.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001	A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder.	PCM	2006	DBLP DOI BibTeX RDF	Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS
19	Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang	Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB).	APCCAS	2006	DBLP DOI BibTeX RDF
19	Insu Song, Guido Governatori	Designing agent chips.	AAMAS	2006	DBLP DOI BibTeX RDF	agent chips, agent architecture, agent programming languages
19	Jung L. Lee, Myung Hoon Sunwoo	Implementation of a Wireless Multimedia DSP Chip for Mobile Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, DSP, instruction
19	Saranyan A. Vigraham, John C. Gallagher	A space saving digital VLSI evolutionary engine for CTRNN-EH devices.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
19	Jaehwan John Lee, Vincent John Mooney III	A novel O(n) parallel banker's algorithm for System-on-a-Chip.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Mathias Halbach, Rolf Hoffmann	Optimal Behavior of a Moving Creature in the Cellular Automata Model.	PaCT	2005	DBLP DOI BibTeX RDF
19	Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee	Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC.	KES (3)	2005	DBLP DOI BibTeX RDF
19	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
19	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
19	Yasuhiro Takahashi, Michio Yokoyama	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
19	Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Ping Dong, Xiangdong Shi, Jiehui Yang	Design of a New Kind of Encryption Kernel Based on RSA Algorithm.	CIS (2)	2005	DBLP DOI BibTeX RDF