The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for phrase boundary-scan (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1988-1990 (21) 1991 (23) 1992 (19) 1993 (18) 1994-1995 (33) 1996 (18) 1997 (17) 1998-1999 (24) 2000-2001 (27) 2002 (17) 2003-2004 (26) 2005-2006 (20) 2007-2009 (19) 2010-2015 (16) 2016-2023 (8)
Publication types (Num. hits)
article(94) inproceedings(211) phdthesis(1)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 406 occurrences of 170 keywords

Results
Found 306 publication records. Showing 306 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
115Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora A Structured Graphical Tool for Analyzing Boundary Scan Violations. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
103Hardy J. Pottinger, Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
85Thomas A. Ziaja, Earl E. Swartzlander Jr. Boundary scan in board manufacturing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Board and system test, boundary scan description language, design-for-test, boundary scan
82Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001 A System Level Boundary Scan Controller Board for VME Applications. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
74T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
70José M. Miranda A BIST and Boundary-Scan Economics Framework. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
70Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski BIST of PCB interconnects using boundary-scan architecture. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
69Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF relay propagation test, multiprocessor systems, Boundary scan
67Nazar S. Haider, Nick Kanopoulos Efficient board interconnect testing using the split boundary scan register. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
64Andrzej Rucinski 0002, Barbara Dziurla-Rucinska Boundary Scan as a Test Solution in Microelectronics Curricula. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF IEEE 1149.4 standard, Education, Boundary scan
61Tian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Jung-Cheun Lien, Melvin A. Breuer An optimal scheduling algorithm for testing interconnect using boundary scan. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Boundary scan, test scheduling, interconnect test
60Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for SRAM cluster interconnect testing at board level. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
60Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang Broadcasting test patterns to multiple circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
59Kenneth P. Parker Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes? Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
59Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier Enhanced Reduced Pin-Count Test for Full-Scan Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
55Maciej Nikodem Boundary Scan Security Enhancements for a Cryptographic Hardware. Search on Bibsonomy EUROCAST The full citation details ... 2009 DBLP  DOI  BibTeX  RDF IEEE 1149, side-channel attacks, countermeasures, boundary scan
55Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi Novel Control Pattern Generators for Interconnect Testing with Boundary Scan. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF BIST, boundary scan, Interconnect testing
55Bernhard Eschermann An implicitly testable boundary scan TAP controller. Search on Bibsonomy J. Electron. Test. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF test controller, BIST, self-test, boundary scan, synthesis for testability, controller design
55Kenneth P. Parker, Stig Oresjo A language for describing boundary scan devices. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF boundary scan testability, VHDL
53Wang-Dauh Tseng, Kuochen Wang Testable Design and Testing of MCMs Based on Multifrequency Scan. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module
52Luís Santos 0005, Mário Zenha Rela Constraints on the Use of Boundary-Scan for Fault Injection. Search on Bibsonomy LADC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
51Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani Testing SoC Interconnects for Signal Integrity Using Boundary Scan. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Integrity Loss Sensor, System-on-Chip Interconnects, Data Compression, Boundary Scan, Signal Integrity
51Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF unscanned interconnects, syndrome test methodology, event driven syndrome simulation, boundary scan environment, faulty syndromes, fault-free syndromes, tolerable error rate, partially scanned PCB, board level testing, test pattern generation, boundary scan testing, test length, MCM, set covering problem, simulation algorithm, weighted random patterns, test cost reduction
51Tong Liu 0007, Fabrizio Lombardi, José Salinas Diagnosis of interconnects and FPICs using a structured walking-1 approach. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
49Frank P. Higgins, Rajagopalan Srinivasan BSM2: Next Generation Boundary-Scan Master. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
48Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for Combinational Cluster Interconnect Testing at Board Level. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
48Matthew L. Fichtenbaum, Gordon D. Robinson Scan test architectures for digital board testers. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF tester architecture, scan, boundary scan
47Janusz Rajski, Jerzy Tyszer, Nadime Zacharia Test Data Decompression for Multiple Scan Designs with Boundary Scan. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF reseeding of LFSRs, multiple scan chains, test data decompression, built-in self-test, design for testability, Boundary scan, scan-based designs
46Wuudiann Ke Hybrid Pin Control Using Boundary-Scan And Its Applications. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Boundary-Scan (B-S), Hybrid Pin Control, Fault Injection, Delay Test
46Jung-Cheun Lien, Melvin A. Breuer Test program synthesis for modules and chips having boundary scan. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
46Don Sterba, Andy Halliday, Don McClean ATPG and diagnostics for boards implementing boundary scan. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF 1149.1, ATPG, diagnostics, boundary scan, JTAG
46R. G. Bennetts, A. Osseyran IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF device test, board test, 1149.1, boundary scan
46Frans Jong, José S. Matos, José M. Ferreira Boundary scan test, test methodology, and fault modeling. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF BST-net, PCB testing, diagnosis, fault modeling, test-pattern generation, boundary scan test
46Colin M. Maunder, Rodham E. Tulloss An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF ANSI/IEEE Std 1149.1, loaded-board test, self-test, boundary scan, JTAG
45Debaditya Mukherjee, Melvin A. Breuer An IEEE 1149.1 Compliant Test Control Architecture. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
44Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
43Jeff Rearick, Sylvia Patterson, Krista Dorner Integrating Boundary Scan into Multi-GHz I/O Circuitry. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Josef Schmid, Timo Schüring, Christoph Smalla Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43W. David Ballew, Lauren M. Streb Board-level boundary scan: regaining observability with an additional IC. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
43R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg Designing and Implementing an Architecture with Boundary Scan. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
41Dilip K. Bhavsar Testing Interconnections to Static RAMs. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
39Mário Zenha Rela, João Carlos Cunha, Carlos Bruno Silva, Luís Ferreira da Silva On the Effects of Errors During Boot. Search on Bibsonomy LADC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF fault-tolerance, embedded systems, fault-injection, boundary-scan, dependability evaluation
35Kaushik De Test methodology for embedded cores which protects intellectual property. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
34Tapan J. Chakraborty Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Bill Eklow, Carl Barnhart, Kenneth P. Parker IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Mike Wondolowski, Ben Bennetts, Adam W. Ley Boundary Scan: The Internet of Test. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Bulent I. Dervisoglu, Mike Ricchetti, William Eklow Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Kanad Chakraborty, Pinaki Mazumder A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
32Ben Bennetts Essential reading for the basics and implementation of boundary scan: Parker, K PThe boundary-scan handbook Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9270 1, £48.00/Dfl. 160.00, pp 282. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
32Yoon-Hwa Choi, Taechul Jung Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices. Search on Bibsonomy ICCAD The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
32Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani Extending JTAG for Testing Signal Integrity in SoCs. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Tapan J. Chakraborty, Chen-Huan Chiang A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Bulent I. Dervisoglu Boundary-Scan Update: IEEE P1149.2 Description and Status Report. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
30Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni An Embedded IDDQ Testing Architecture and Technique. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
30Hans A. R. Manhaeve, Stefaan Kerckenaere An On-Chip Detection Circuit for the Verification of IC Supply Connections. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor
30Najmi T. Jarwala Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF module test, design-for-testability, boundary-scan
30Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core test, design-for-testability, BIST, scan, boundary scan, test bus
30Nur A. Touba, Bahram Pouya Testing Embedded Cores Using Partial Isolation Rings. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
30Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF MTM Bus, Boundary Scan, Hierarchical Testing
30Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer A Design For Test Perspective on I/O Management. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF I/O pads, High Level Synthesis, Design For Test, Boundary Scan
29Jing Wang, Shengbing Zhang, Zhang Meng Testing of a 32-bit High Performance Embedded Microprocessor. Search on Bibsonomy SIES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. Search on Bibsonomy J. Electron. Test. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
26Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri Test-mode-only scan attack using the boundary scan chain. Search on Bibsonomy ETS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
26Stephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood Hierarchical boundary-scan: a Scan Chip-Set solution. Search on Bibsonomy ITC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Anthony P. Ambler The application and use of boundary scan: Bleeker, H, van den Eijnden, P and de Jong, FBoundary-scan test - a practical approach Kluwer Academic (1992) ISBN 0 7923 9296 5, £50.75, pp 222. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
25Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela FPGA-Based Boundary-Scan Bist. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Yang Jiangping, Li Guixiang, Wang Wanglei A model of VLSI interconnect test based on boundary scan. Search on Bibsonomy ICARCV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Bill Eklow, Carl Barnhart, Kenneth P. Parker IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Bradford G. Van Treuren, José M. Miranda Embedded Boundary Scan. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Tek Jau Tan, Chung-Len Lee Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Oscillation test, Delay testing, System test, SOC testing, Embedded testing
25Sungju Park, Taehyung Kim A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Hyunjin Kim, Jongchul Shin, Sungho Kang 0001 An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur Delay test of chip I/Os using LSSD boundary scan. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Adam Kristof Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
25Colin M. Maunder A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
24Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan ScanBist: A Multifrequency Scan-Based BIST Method. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
23Dave Stang, Ramaswami Dandapani An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
21Jari Hannu, Markku Moilanen Methods of Testing Discrete Semiconductors in the 1149.4 Environment. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 1149.4, Discrete semiconductors, Boundary scan
21Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
21Franc Novak, Anton Biasizzo Security Extension for IEEE Std 1149.1. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF security, test, boundary-scan
21Carl Jeffrey, Reuben Cutajar, Andrew Richardson 0001, Stephen Prosser, M. Lickess, Stephen Riches The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF IEEE1149.4, IDR, fault tolerance, boundary scan, on-line monitoring
21Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou Intrinsic response for analog module testing using an analog testability bus. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
21Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen Peak-power reduction for multiple-scan circuits during test application. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
21Irith Pomeranz, Sudhakar M. Reddy Reducing test application time for full scan circuits by the addition of transfer sequences. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
21Chauchin Su, Shyh-Jye Jou Decentralized BIST Methodology for System Level Interconnects. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF interconnect, BIST, DFT, boundary scan
21Chanyutt Arjhan, Raghvendra G. Deshmukh A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
21Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang Using a single input to support multiple scan chains. Search on Bibsonomy ICCAD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF boundary scan (IEEE 1149.1) and test compaction, test generation, design for testability, scan based design
21Joel A. Jorgenson, Russell J. Wagner Design-For-Test in a Multiple Substrate Multichip Module. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Multichip Module (MCM) Test, Known-Good Die (KGD), Ball Grid Array (BGA), Built-In-Self-Test (BIST), boundary-scan
21Thomas M. Storey, Bruce McWilliam A Test Methodology for High Performance MCMs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing
21Ken Posse A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fault diagnosis, Boundary-Scan, Multichip Module, MCM, interconnect testing, manufacturing defects
21T. Haulin Built-in parametric test for controlled impedance I/Os. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
21Johan Verfaillie, Didier Haspeslagh A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mixed-signal DFT, mixed-signal boundary scan, modular mixed-signal test
21Robert B. Norwood, Edward J. McCluskey Synthesis-for-scan and scan chain ordering. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
21Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda Scan insertion criteria for low design impact. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
Displaying result #1 - #100 of 306 (100 per page; Change: )
Pages: [1][2][3][4][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license