Search results for "built-in-testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
40	Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio	An On-Chip Spectrum Analyzer for Analog Built-In Testing.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	analog IC test, built-in testing, frequency response, switched-capacitor circuits
37	Kozo Kinoshita, Kewal K. Saluja	Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity
37	Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka	A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	self-verification, error-detection ability, group-parity prediction checker, self-testing, Built-in testing, duplication, self-checking checker, fault-detection ability
32	Sampath Rangarajan, Donald S. Fussell, Miroslaw Malek	Built-In Testing of Integrated Circuit Wafers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	integrated circuit wafers, silicon wafers, VLSI, integrated circuit testing, automatic testing, built-in testing, production testing
32	El Mostapha Aboulhamid, Eduard Cerny	A Class of Test Generators for Built-In Testing.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	test set compression, Anti-self-dual functions, test generator, coding, built-in testing
28	Irena Pavlova, Mikael Åkerholm, Johan Fredriksson	Application of built-in-testing in component-based embedded systems.	ROSATEA	2006	DBLP DOI BibTeX RDF
23	Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio	A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers.	VTS	2005	DBLP DOI BibTeX RDF
23	Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio	On-chip spectrum analyzer for built-in testing analog ICs.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
21	Sami Beydeda	Research in testing COTS components - built-in testing approaches.	AICCSA	2005	DBLP DOI BibTeX RDF
21	Kozo Kinoshita, Kewal K. Saluja	Built-in Testing of Memory Using On-chip Compact Testing Scheme.	ITC	1984	DBLP BibTeX RDF
16	Sheng Zhang 0008, Sharad C. Seth, Bhargab B. Bhattacharya	Efficient Test Compaction for Pseudo-Random Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	built-in testing, test-data compression, Test compaction, pseudo-random testing
16	Irith Pomeranz, Sudhakar M. Reddy	A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	scan circuits, Built-in testing, Cartesian product
16	Érika F. Cota, Fernanda Lima 0001, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis 0001	Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	integrated circuits radiation effects, aerospace testing, built-in-testing, microprocessor testing
16	Hal Wasserman, Manuel Blum 0001	Software reliability via run-time result-checking.	J. ACM	1997	DBLP DOI BibTeX RDF	self-correcting, fault tolerance, debugging, Fourier transform, concurrent error detection, built-in testing, result-checking
16	Manuel Blum 0001, Hal Wasserman	Reflections on the Pentium Bug.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Pentium, fault tolerance, reliability, verification, concurrent error detection, Built-in testing, result-checking
16	Wojciech Maly, Marek J. Patyra	Design of ICs applying built-in current testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	BIC-testing, Built-in testing, current testing
16	William H. McAnney, Jacob Savir	Built-In Checking of the Correct Self-Test Signature.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	self-test signature, initial value, signature register, single observation, logic testing, automatic testing, built-in testing
16	Melvin A. Breuer, Asad A. Ismaeel	Roving Emulation as a Fault Detection Mechanism.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	digital systems testing, roving emulation, simulation, fault detection, emulation, Built-in testing, error latency
16	Kewal K. Saluja, Kozo Kinoshita	Test Pattern Generation for API Faults in RAM.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	static pattern-sensitive faults, fault detection, Built-in testing, random-access memory, pattern-sensitive faults
16	Manjiri L. Karandikar, Snehprabha Lad	A Review of On-Chip Spectral Analysis for Built-In Testing Using FFT Engine.	ICETET	2015	DBLP DOI BibTeX RDF
16	Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim	Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González 0001, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo	Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes.	MWSCAS	2014	DBLP DOI BibTeX RDF
16	Abhijit Chatterjee, Donghoon Han, Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Hyun Woo Choi, Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhilash Goyal, Deuk Lee, Madhavan Swaminathan	Iterative built-in testing and tuning of mixed-signal/RF systems.	ICCD	2009	DBLP DOI BibTeX RDF
16	Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, José Silva-Martínez	Non-invasive RF built-in testing using on-chip temperature sensors.	ITC	2009	DBLP DOI BibTeX RDF
16	Daniel Brenner, Colin Atkinson 0001, Rainer Malaka, Matthias Merdes, Barbara Paech, Dima Suliman	Reducing verification effort in component-based software engineering through built-in testing.	Inf. Syst. Frontiers	2007	DBLP DOI BibTeX RDF	Run-time testing, MORABIT, Built-in test, Integration test
16	Daniel Brenner	Enabling Run-Time System Verification through Built-In Testing.	TAIC PART	2006	DBLP DOI BibTeX RDF
16	Daniel Brenner, Colin Atkinson 0001, Barbara Paech, Rainer Malaka, Matthias Merdes, Dima Suliman	Reducing Verification Effort in Component-Based Software Engineering through Built-In Testing.	EDOC	2006	DBLP DOI BibTeX RDF
16	Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio	An On-Chip Transfer Function Characterization System for Analog Built-in Testing.	VTS	2004	DBLP DOI BibTeX RDF
16	Derek Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly	Current sensing for built-in testing of CMOS circuits.	ICCD	1988	DBLP DOI BibTeX RDF
16	Eiji Fujiwara, Kohji Matsuoka	A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF
16	Hideo Tamamoto, Hirotomo Sakusabe, Yuichi Narita	A built-in testing scheme for ic memories by considering address decoder and cell array separately.	Syst. Comput. Jpn.	1987	DBLP DOI BibTeX RDF
16	Parag K. Lala	On Built-In Testing of VLSI Chips.	ITC	1986	DBLP BibTeX RDF
16	El Mostapha Aboulhamid, Eduard Cerny	Built-In Testing of One-Dimensional Unilateral Iterative Arrays.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
16	Wilfried Daehn, Joachim Mucha	Hardware Test Pattern Generation for Built-In Testing.	ITC	1981	DBLP BibTeX RDF
13	Wen-Ben Jone, Anita Gleason	Analysis of Hamming count compaction scheme.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	index vector, spectral coefficients, Built-in self test, compaction, syndrome
10	Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian	A Test Interface for Built-In Test of Non-Isolated Scanned Cores.	VTS	2003	DBLP DOI BibTeX RDF
10	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Wen-Ben Jone, Christos A. Papachristou, M. Pereira	A Scheme for Overlaying Concurrent Testing of VLSI Circuits.	DAC	1989	DBLP DOI BibTeX RDF
5	Mohammad Azam, Krishna R. Pattipati, Ann Patterson-Hine	Optimal sensor allocation for fault detection and isolation.	SMC (2)	2004	DBLP DOI BibTeX RDF