Search results for "c-to-gates"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
96	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
76	Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
68	Nathan O. Scott, Gerhard W. Dueck	Pairwise decomposition of toffoli gates in a quantum circuit.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	elementary quantum gates, synthesis, minimization, reversible logic, quantum circuits
64	Shoujue Wang, Xunwei Wu, Hongjuan Feng	The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors.	ISMVL	1995	DBLP DOI BibTeX RDF	high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
56	Stephen S. Bullock, Igor L. Markov	An arbitrary twoqubit computation In 23 elementary gates or less.	DAC	2003	DBLP DOI BibTeX RDF	CNOT, circuit decomposition, elementary gates, lie theory, optimization, algorithms, lower bounds, synthesis, quantum circuits, qubit
54	Vincenzo Catania, Marco Russo	Analog gates for a VLSI fuzzy processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits
53	Ahmed N. Sulaiman, Patrick Olivier	Attribute gates.	UIST	2008	DBLP DOI BibTeX RDF	crossing interfaces, large interactive displays, tabletop territories, pen-based input, digital tabletops, user interface components
51	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Toffoli network synthesis with templates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
51	Mawahib Hussein Sulieman	On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations.	NanoNet	2009	DBLP DOI BibTeX RDF	Reliability, CMOS, threshold voltage, gates
47	Stasys Jukna	Finite Limits and Monotone Computations: The Lower Bounds Criterion.	CCC	1997	DBLP DOI BibTeX RDF	real gates, lower bounds, threshold gates, monotone circuits
47	Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
47	Kristoffer Arnsfelt Hansen	Depth Reduction for Circuits with a Single Layer of Modular Counting Gates.	CSR	2009	DBLP DOI BibTeX RDF
47	Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001	Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.	ICCAD	2007	DBLP DOI BibTeX RDF
47	Rolando Ramírez Ortiz, John P. Knight	Compatible cell connections for multifamily dynamic logic gates.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
47	Sudhakar Bobba, Ibrahim N. Hajj	Current-Mode Threshold Logic Gates.	ICCD	2000	DBLP DOI BibTeX RDF
47	Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli	ORCA a Sea-of-Gates Place and Route System.	DAC	1989	DBLP DOI BibTeX RDF
46	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
46	Wolfgang Maass 0001, Georg Schnitger, Eduardo D. Sontag	On the Computational Power of Sigmoid versus Boolean Threshold Circuits	FOCS	1991	DBLP DOI BibTeX RDF	polynomially bounded weights, sigmoid threshold gates, smooth threshold gates, depth 2 circuits, Boolean threshold circuits, constant size circuits, Boolean threshold gates, polynomial size sigmoid threshold circuits, Boolean functions, computational power, constant depth circuits
45	Shane Greenstein	The Long Arc Behind Bill Gates' Wealth.	IEEE Micro	2008	DBLP DOI BibTeX RDF	William Gates, antitrust, economics, competition, browser, Microsoft, bundling
45	Thomas Flohr 0002	Defining Suitable Criteria for Quality Gates.	IWSM/Metrikon/Mensura	2008	DBLP DOI BibTeX RDF	Practical measurement application, Measurement acceptance, Quality Gates
44	Youngja Park, Christopher S. Gates, Stephen C. Gates	Estimating Asset Sensitivity by Profiling Users.	ESORICS	2013	DBLP DOI BibTeX RDF
43	Hung Chi Lai, Saburo Muroga	Minimum Parallel Binary Adders with NOR (NAND) Gates.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
43	Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga	Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	n-p-n-equivalence classes, four variable switching functions, optimal networks, logical design, branch-and-bound method, AND gates, OR gates
41	Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi	Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Testing, Emerging technologies, Reversible computing, QCA
41	Asif Islam Khan, Nadia Nusrat, Samira Manabi Khan, Masud Hasan, Mozammel H. A. Khan	Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates.	ISMVL	2007	DBLP DOI BibTeX RDF
41	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan	On Universality of General Reversible Multiple-Valued Logic Gates.	ISMVL	2004	DBLP DOI BibTeX RDF
40	Marek A. Perkowski, Nouraddin Alhagi, Martin Lukac, Neha Saxena, Scott Blakely	Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates.	ISMVL	2010	DBLP DOI BibTeX RDF	pseudo-reversible logic gates, reversible circuits
40	Mozammel H. A. Khan, Marek A. Perkowski	GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits.	ISMVL	2007	DBLP DOI BibTeX RDF
40	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Synthesis of Fredkin-Toffoli reversible networks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
40	Märt Saarepera, Tomohiro Yoneda	A Self-Timed Implementation of Boolean Functions.	ASYNC	1999	DBLP DOI BibTeX RDF
40	Kerry S. Lowe, P. Glenn Gulak	A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
39	Xinliang Zhang, Jing Xu, Jianji Dong, Dexiu Huang	All-Optical Logic Gates Based on Semiconductor Optical Amplifiers and Tunable Filters.	OSC	2009	DBLP DOI BibTeX RDF	all-optical logic gates, semiconductor optical amplifiers (SOAs), delay interferometer, bandpass filter
39	Shane Greenstein	The Long Arc Behind Bill Gates' Wealth, Part 2.	IEEE Micro	2008	DBLP DOI BibTeX RDF	William Gates, antitrust, economics, competition, browser, Microsoft, bundling
38	Francisco J. Artigas, Soon Ae Chun, Yogi Sookhu	Real-time ocean surge warning system, meadowlands district of New Jersey.	D.GO	2009	DBLP BibTeX RDF	emergency management system, real-time ocean surge warnings, tide gates, sensor network, flood, information dissemination, emergency management, sensor system
38	David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah	Timing verification of sequential domino circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	domino gates, sequential domino circuits, static timing verification, logic testing, input signals
36	Yuri B. Boiko, Gabriel A. Wainer	Modeling quantum dot devices in Cell-DEVS environment.	SpringSim	2008	DBLP DOI BibTeX RDF	majority vote gates, quantum wire, cellular automata, discrete event simulation, quantum dot, XOR gates, cell-DEVS, quantum automata
36	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
36	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
36	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
35	Falk Unger	Noise Threshold for Universality of Two-Input Gates.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
35	Yang Zhao 0001, Tao Xu 0002, Krishnendu Chakrabarty	Digital Microfluidic Logic Gates.	NanoNet	2008	DBLP DOI BibTeX RDF	microfluidic computing, digital microfluidics, logic gate
35	Krishna Santhanam, Kenneth S. Stevens	Dynamic gates with hysteresis and configurable noise tolerance.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
35	Jose M. Marulanda, Ashok Kumar Srivastava, Ashwani K. Sharma	Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs).	SBCCI	2007	DBLP DOI BibTeX RDF	CNT-logic, cut-off frequency, small signal model, transfer characteristics, carbon nanotubes
35	Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao 0001	An efficient method to identify critical gates under circuit aging.	ICCAD	2007	DBLP DOI BibTeX RDF
35	Xiaoyu Song, Guowu Yang, Marek A. Perkowski, Yuke Wang	Algebraic Characterization of Reversible Logic Gates.	Theory Comput. Syst.	2006	DBLP DOI BibTeX RDF
35	Josep Carmona 0001, Jordi Cortadella, Yousuke Takada, Ferdinand Peper	From molecular interactions to gates: a systematic approach.	ICCAD	2006	DBLP DOI BibTeX RDF	nanocascades, formal methods, nanocomputing
35	Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas	A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.	DFT	2006	DBLP DOI BibTeX RDF
35	Wladyslaw Homenda, Witold Pedrycz	Balanced Fuzzy Gates.	RSCTC	2006	DBLP DOI BibTeX RDF
35	Arkadev Chattopadhyay, Kristoffer Arnsfelt Hansen	Lower Bounds for Circuits with Few Modular and Symmetric Gates.	ICALP	2005	DBLP DOI BibTeX RDF
35	Stefan Mangard, Thomas Popp, Berndt M. Gammel	Side-Channel Leakage of Masked CMOS Gates.	CT-RSA	2005	DBLP DOI BibTeX RDF
35	M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu	Identification of Gates for Covering all Critical Paths.	MTV	2004	DBLP DOI BibTeX RDF
35	Peter M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire	A Binary Multiplier Using RTD Based Threshold Logic Gates.	IWANN (2)	2003	DBLP DOI BibTeX RDF
35	Pawel Kerntopf	Synthesis of Multipurpose Reversible Logic Gates.	DSD	2002	DBLP DOI BibTeX RDF
35	Alexis De Vos, Bart Desoete, Artur Adamski, Piotr Pietrzak, Maciej Sibínski, Tomasz Widerski	Design of Reversible Logic Circuits by Means of Control Gates.	PATMOS	2000	DBLP DOI BibTeX RDF
35	Mayukh Bhattacharya, Pinaki Mazumder	Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Quantum devices, Digital circuits, Resonant Tunneling Diode, Noise margin, Threshold gate
35	Nicholas Pippenger	Invariance of complexity measures for networks with unreliable gates.	J. ACM	1989	DBLP DOI BibTeX RDF
35	G. D. Adams, Carlo H. Séquin	Template Style Considerations for Sea-of-Gates Layout Generation.	DAC	1989	DBLP DOI BibTeX RDF
35	Donald L. Richards	Efficient Exercising of Switching Elements in Nets of Identical Gates.	J. ACM	1973	DBLP DOI BibTeX RDF
34	Kazuo Iwama, Hiroki Morizumi, Jun Tarui	Negation-Limited Complexity of Parity and Inverters.	Algorithmica	2009	DBLP DOI BibTeX RDF	Negation-limited circuit, Parity function, Inversion complexity, Gate elimination, Circuit complexity, Inverter
34	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	Dual-threshold pass-transistor logic design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual threshold, pass transistor, low power, leakage
34	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
34	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
34	Li Ding 0002, Pinaki Mazumder	On circuit techniques to improve noise immunity of CMOS dynamic logic.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
34	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Fredkin/Toffoli Templates for Reversible Logic Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
34	Chuen-Der Huang, I-Fang Chung, Nikhil R. Pal, Chin-Teng Lin	Machine Learning for Multi-class Protein Fold Classification Based on Neural Networks with Feature Gating.	ICANN	2003	DBLP DOI BibTeX RDF
34	Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors.	ISMVL	2000	DBLP DOI BibTeX RDF
34	Vince Grolmusz, Gábor Tardos	Lower Bounds for (MOD p - MOD m) Circuits.	FOCS	1998	DBLP DOI BibTeX RDF
34	Sorin Cotofana, Stamatis Vassiliadis	On the Design Complexity of the Issue Logic of Superscalar Machines.	EUROMICRO	1998	DBLP DOI BibTeX RDF
34	Rajesh S. Parthasarathy, Ramalingam Sridhar	Double Pass Transistor Logic for High Performance Wave Pipeline Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF
34	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
34	Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider	A comparative study of CMOS gates with minimum transistor stacks.	SBCCI	2007	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates
34	Frank Sill, Jiaxi You, Dirk Timmermann	Design of mixed gates for leakage reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	mixed gates, leakage current, threshold voltage, gate leakage
34	Markus Dichtl, Jovan Dj. Golic	High-Speed True Random Number Generation with Logic Gates Only.	CHES	2007	DBLP DOI BibTeX RDF	generalized ring oscillators, true randomness, Random number generation, logic gates, ring oscillators
34	Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee	A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates.	DAC	2006	DBLP DOI BibTeX RDF	dynamic gates, keeper design, reliability, VLSI, robustness, low-power design, process variation
34	Michal Koucký 0001, Pavel Pudlák, Denis Thérien	Bounded-depth circuits: separating wires from gates.	STOC	2005	DBLP DOI BibTeX RDF	communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates
34	Joshua Berman, Arthur Drisko, François Lemieux, Cristopher Moore, Denis Thérien	Circuits and Expressions with NOn-Associative Gates.	CCC	1997	DBLP DOI BibTeX RDF	non-associative gates, non-associative groupoid, polyabelian groupoids, arbitrary Boolean functions, NC/sup 1/-complete, CIRCUIT VALUE, Boolean functions, multiplication, P-complete, EXPRESSION EVALUATION
32	Oriol Roig, Jordi Cortadella, Enric Pastor	Hierarchical gate-level verification of speed-independent circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates
32	Sandip Kundu, Sudhakar M. Reddy	Robust tests for parity trees.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	linear gates, parity trees, URTS, robust tests, test length
31	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
31	Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda	High-speed low-power logic gates using floating gates.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
30	Guilu Long 0001, Yang Liu	Duality quantum computing.	Frontiers Comput. Sci. China	2008	DBLP DOI BibTeX RDF	duality computer, duality quantum computer, duality parallelism, duality gates, duality mode, generalized quantum gates, combiner, divider
30	Michel Renovell, P. Huc, Yves Bertrand	The concept of resistance interval: a new parametric model for realistic resistive bridging fault.	VTS	1995	DBLP DOI BibTeX RDF	electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
30	Shyue-Win Wei	A Systolic Power-Sum Circuit for GF(2^m).	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic power-sum circuit, power-sum circuit, error correction codes, error-correcting codes, finite field, systolic arrays, decoding, logic circuits, logic gates, logical gates
30	Ingo Wegener	Comments on "A Characterization of Binary Decision Diagrams".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	EXOR gates, NEXOR gates, free BDDs, ordered BDDs, repeated BDDs, computational complexity, complexity, Boolean functions, binary decision diagrams, decision tables, combinatorial circuits
30	Niraj K. Jha	Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers
30	Eric Allender	A Note on the Power of Threshold Circuits	FOCS	1989	DBLP DOI BibTeX RDF	unbounded-fan-in circuits, depth-three threshold circuits, polynomial hierarchy, threshold circuits, AND gates, OR gates
30	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
30	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
30	Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann	Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.	SBCCI	2009	DBLP DOI BibTeX RDF	gate oxide breakdown, reliability, integrated circuit design, redundant systems
30	Ashish Goel, Morteza Ibrahimi	Renewable, Time-Responsive DNA Logic Gates for Scalable Digital Circuits.	DNA	2009	DBLP DOI BibTeX RDF
30	James Donald, Niraj K. Jha	Reversible logic synthesis with Fredkin and Peres gates.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Quantum computing, reversible logic
30	David Guerrero Martos, Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo	Static Power Consumption in CMOS Gates Using Independent Bodies.	PATMOS	2007	DBLP DOI BibTeX RDF
30	Mario Vélez, Juan Ospina	Universal Quantum Gates Via Yang-Baxterization of Dihedral Quantum Double.	ICANNGA (1)	2007	DBLP DOI BibTeX RDF
30	Arkadev Chattopadhyay, Navin Goyal, Pavel Pudlák, Denis Thérien	Lower bounds for circuits with MOD_m gates.	FOCS	2006	DBLP DOI BibTeX RDF
30	Kristian Granhaug, Snorre Aunet, Tor Sverre Lande	Body-bias regulator for ultra low power multifunction CMOS gates.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson	CMOS Realization of Online Testable Reversible Logic Gates.	ISVLSI	2005	DBLP DOI BibTeX RDF
30	Kazuyuki Amano, Akira Maruoka	On the Complexity of Depth-2 Circuits with Threshold Gates.	MFCS	2005	DBLP DOI BibTeX RDF
30	Emanuele Viola	Pseudorandom Bits for Constant Depth Circuits with Few Arbitrary Symmetric Gates.	CCC	2005	DBLP DOI BibTeX RDF
30	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF