Search results for "carry-ripple"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
38	Jean-Luc Beuchat, Jean-Michel Muller	Automatic Generation of Modular Multipliers for FPGA Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
34	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
34	Hung Chi Lai, Saburo Muroga	Minimum Parallel Binary Adders with NOR (NAND) Gates.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
24	Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Partially Duplicated Code-Disjoint Carry-Skip Adder.	DFT	2002	DBLP DOI BibTeX RDF
24	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
19	Viv A. Bartlett, Andrew G. Dempster	Using carry-save adders in low-power multiplier blocks.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
19	Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme	Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
19	Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy	(Quasi-) Linear Path Delay Fault Tests for Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
15	Rodney Van Meter, W. J. Munro, Kae Nemoto, Kohei M. Itoh	Arithmetic on a distributed-memory quantum multicomputer.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	quantum computer architecture, Quantum computing
15	Rodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M. Itoh	Distributed Arithmetic on a Quantum Multicomputer.	ISCA	2006	DBLP DOI BibTeX RDF

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