Search results for "chipset"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
132	Ravishankar K. Iyer	Performance implications of chipset caches in web servers.	ISPASS	2003	DBLP DOI BibTeX RDF
100	Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi	A prototype chipset for a large scaleable ATM switching node.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	prototype chipset, large scaleable ATM switching node, static logic, packet headers storage, dynamic logic, register file, CMOS digital integrated circuits, banyan network, CMOS IC, 1 micron
69	Sherri Sparks, Shawn Embleton, Cliff Changchun Zou	A chipset level network backdoor: bypassing host-based firewall & IDS.	AsiaCCS	2009	DBLP DOI BibTeX RDF	network backdoor, rootkit, hardware security
69	Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng	The Blackford Northbridge Chipset for the Intel 5000.	IEEE Micro	2007	DBLP DOI BibTeX RDF	platform architecture, dual-processor system, northbridge chipset, I/O bridges, FB-DIMM memory technology, low-power design, shared memory
54	Saikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar	Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25µm CMOS.	VLSI Design	2003	DBLP DOI BibTeX RDF
46	William Lloyd Bircher, Lizy K. John	Power phase variation in a commercial server workload.	ISLPED	2006	DBLP DOI BibTeX RDF	chipset, commercial workload characterization, memory, power, microprocessor, disk, program phase
45	Debendra Das Sharma	Intel® 5520 chipset: An I / O hub chipset for server, workstation, and high end desktop.	Hot Chips Symposium	2009	DBLP DOI BibTeX RDF
38	Jeffrey M. Gilbert, Chinh H. Doan, Sohrab Emami, C. Bernard Shung	A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset.	IEEE Micro	2008	DBLP DOI BibTeX RDF	uncompressed, HDMI, multimedia, networking, wireless, video, CMOS, high-definition, 60 GHz
38	Boo-Young Choi, Jung-Won Han, Sung Min Park 0001, Kang-Yeob Park, Wonseok Oh 0003, J.-C. Choi	A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Michel Sarlotte, Bernard Candaele, Jérôme Quévremont, D. Merel	Embedded Software in Digital AM-FM Chipset.	DATE	2003	DBLP DOI BibTeX RDF
38	Sung-Eun Kim, Seong-Jun Song, Sung Min Park 0001, Hoi-Jun Yoo	CMOS optical receiver chipset for gigabit Ethernet applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
38	Uwe Fassnacht, Jürgen Schietke	Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset.	DATE	1998	DBLP DOI BibTeX RDF	Timing, static timing analysis, timing optimization
38	Jürgen Koehl, Ulrich Baur, Thomas Ludwig 0004, Bernhard Kick, Thomas Pflueger	A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.	DATE	1998	DBLP DOI BibTeX RDF
38	Mojy Chian, Gregg Croft, Steve Jost, Patrick Landy, Brent A. Myers, John Prentice, Doug Schultz	IC implementation challenges of a 2.4 GHz wireless LAN chipset.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
31	Jiho Ryu, Jeongkeun Lee, Sung-Ju Lee, Taekyoung Kwon 0001	Revamping the IEEE 802.11a PHY simulation models.	MSWiM	2008	DBLP DOI BibTeX RDF	physical layer capture, simulations, interference, carrier sensing, IEEE 802.11a
31	François Abel, Cyriel Minkenberg, Ilias Iliadis, Antonius P. J. Engbersen, Mitchell Gusat, Ferdinand Gramsamer, Ronald P. Luijten	Design issues in next-generation merchant switch fabrics.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	combined Input and crosspoint Queueing (CICQ), interconnection networks, packet switching, buffered crossbar
31	Oleg Panfilov, Antonio Turgeon, Ron Hickling, Lloyd Linder	Direct Conversion Transceivers as a Promising Solution for Building Future Ad-Hoc Networks.	NEW2AN	2007	DBLP DOI BibTeX RDF	Direct RF conversion, frequency agility, protocol independence, opportunistic networks, network connectivity, dynamic spectrum allocation
31	Gary Gostin, Jean-Francois Collard, Kirby Collins	The architecture of the HP Superdome shared-memory multiprocessor.	ICS	2005	DBLP DOI BibTeX RDF
31	Ravi R. Iyer 0001	Characterization and Evaluation of Cache Hierarchies for Web Servers.	World Wide Web	2004	DBLP DOI BibTeX RDF	chipsets, snoop filters, simulation, performance evaluation, memory hierarchy, web servers, cache coherence, shared caches, commercial workloads
31	Faye A. Briggs, Suresh Chittor, Kai Cheng	Micro-architecture techniques in the intel E8870 scalable memory controller.	WMPI	2004	DBLP DOI BibTeX RDF	distributed coherency, transaction flows, scalability, memory latency
31	Xiaojun Yang, Lili Guo, Peiheng Zhang, Ninghui Sun	Design of System Area Network Interface Card Based on Intel IOP310.	ICESS	2004	DBLP DOI BibTeX RDF
31	Linda Dailey Paulson	The Ins and Outs of New Local I/O Trends.	Computer	2003	DBLP DOI BibTeX RDF
31	D. J. Beauregard, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Savio N. Chau, Leon Alkalai	Error-Injection-Based Failure Characterization of the IEEE 1394 Bus.	IOLTS	2003	DBLP DOI BibTeX RDF
31	Shen-Chuan Tai, Chuen-Ching Wang, Jui-Lin Wang	Circuit-Sharing Design between FFT and IMDCT with Pipeline Structure for DAB Receiver .	AINA	2003	DBLP DOI BibTeX RDF
22	Kiichi Niitsu, Koki Fukushima, Yuichi Hiraoka, Hidenori Urawa, Yutaka Ozawa, Yuya Osaki, Masaya Kaneko, Jin Nakamura, Hideo Yoshikawa	A 65-nm CMOS Millimeter-Wave Ear-Worn Non-Invasive Continuous Glucose Monitoring Chipset Using a 0.17mm2 72mW Transmitter and a 0.75mm2 80mW Direct-Conversion Receiver.	LASCAS	2024	DBLP DOI BibTeX RDF
22	Vitor Costa, Murilo R. Perleberg, Luciano Agostini, Marcelo Schiavon Porto	Coding Efficiency and Time Evaluation of Apple A15 Bionic Chipset HEVC Encoder.	LASCAS	2024	DBLP DOI BibTeX RDF
22	Yanshu Guo, Qichun Liu, Wenqiang Huang, Yaoyu Li, Tian Tian, Nan Wu, Siqi Zhang, Tiefu Li, Zhihua Wang 0001, Ning Deng 0008, Yuanjin Zheng, Hanjun Jiang	29.4 A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation.	ISSCC	2024	DBLP DOI BibTeX RDF
22	Yuhan Hou, Yi Zhu, Xiao Wu, Yinfei Li, Timothy H. Lucas, Andrew G. Richardson, Xilin Liu	33.4 A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-End and Explainable AI for Memory Studies in Freely Behaving Monkeys.	ISSCC	2024	DBLP DOI BibTeX RDF
22	MohammadAli Shaeri, Uisub Shin, Amitabh Yadav, Riccardo Caramellino, Gregor Rainer, Mahsa Shoaran	33.3 MiBMI: A 192/512-Channel 2.46mm² Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes.	ISSCC	2024	DBLP DOI BibTeX RDF
22	Zekun Li 0005, Jixin Chen, Huanbo Li, Jiayang Yu, Yuxiang Lu, Rui Zhou, Zhe Chen, Wei Hong 0002	A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data Rate Communication in 0.13-µm SiGe BiCMOS.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
22	Haoran Pu, Omid Malekzadeh-Arasteh, Ahmad Reza Danesh, Zoran Nenadic, An H. Do, Payam Heydari	A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
22	Pen-Jui Peng, Po-Lin Lee, Hsiang-En Huang, Wei-Jian Huang, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng	A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
22	Mingran Yang, Alex Baban, Valery Kugel, Jeff Libby, Scott Mackie, Swamy Sadashivaiah Renu Kananda, Chang-Hong Wu, Manya Ghobadi	Using trio: juniper networks' programmable chipset - for emerging in-network applications.	SIGCOMM	2022	DBLP DOI BibTeX RDF
22	Mohamed Elkhouly, Jaegeun Ha, Michael J. Holyoak, David Hendry, Mustafa Sayginer, Ryan Enright, Ioannis Kimionis, Yves Baeyens, Shahriar Shahramian	Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules.	ISSCC	2022	DBLP DOI BibTeX RDF
22	Jin Choi, Seohwan Yoo, Hayeon Park, Chang-Gun Lee	Performance Analysis of an Embedded Chipset on a Multi-screen based Automotive Applications Environment.	ICICT	2022	DBLP DOI BibTeX RDF
22	Xing Zhou, Zhilei Xu, Cong Wang, Mingyu Gao 0001	PPMLAC: high performance chipset architecture for secure multi-party computation.	ISCA	2022	DBLP DOI BibTeX RDF
22	Sona Carpenter, Herbert Zirath, Zhongxia Simon He, Mingquan Bao	A fully integrated D-band direct-conversion I/Q transmitter and receiver chipset in SiGe BiCMOS technology.	J. Commun. Networks	2021	DBLP DOI BibTeX RDF
22	Yuwei Wang, Hongrui Luo, Yang Chen, Zihao Jiao, Quan Sun, Lei Dong, Xinlei Chen, Xiaofei Wang, Hong Zhang 0009	A Closed-Loop Neuromodulation Chipset With 2-Level Classification Achieving 1.5-Vpp CM Interference Tolerance, 35-dB Stimulation Artifact Rejection in 0.5ms and 97.8%-Sensitivity Seizure Detection.	IEEE Trans. Biomed. Circuits Syst.	2021	DBLP DOI BibTeX RDF
22	Shinan Liu, Xiang Cheng, Hanchao Yang, Yuanchao Shu, Xiaoran Weng, Ping Guo 0007, Kexiong Curtis Zeng, Gang Wang 0011, Yaling Yang	Stars Can Tell: A Robust Method to Defend against GPS Spoofing Attacks using Off-the-shelf Chipset.	USENIX Security Symposium	2021	DBLP BibTeX RDF
22	Wilson Feng, Rasool Maghareh, Kai-Ting Amy Wang	Extending DPC++ with Support for Huawei Ascend AI Chipset.	IWOCL	2021	DBLP DOI BibTeX RDF
22	Nhut-Thanh Tran, Masayuki Fukuzawa	A Portable Spectrometric System for Quantitative Prediction of the Soluble Solids Content of Apples with a Pre-calibrated Multispectral Sensor Chipset.	Sensors	2020	DBLP DOI BibTeX RDF
22	Xiaojun Bi 0003, Jian Li, Zhen Gu, Bo Tang, Chaodi Sheng, Yan Yang, Qinfen Xu	High Sensitivity and Dynamic-Range 25 Gbaud Silicon Receiver Chipset With Current-Controlled DC Adjustment Path and Cube-Shape Ge-on-Si PD.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
22	Marco Grassi, Massimo Gandola, Filippo Mele, Giuseppe Bertuccio, Piero Malcovati, F. Fuschino, R. Campana, C. Labanti, Massimiliano Fiorini, Yuri Evangelista, Raffaele Piazzolla, Marco Feroci, G. Zampa, N. Zampa, A. Rachevski, Pierluigi Bellutti, Giacomo Borghi, E. Demenev, Francesco Ficorella, A. Picciotto, N. Zorzi, Irina Rashevskaya, Andrea Vacchi, Fabrizio Fiore, L. Burderi	X-/γ-Ray Detection Instrument for the HERMES Nano-Satellites Based on SDDs Read-Out by the LYRA Mixed-Signal ASIC Chipset.	I2MTC	2020	DBLP DOI BibTeX RDF
22	Yuwei Wang, Quan Sun, Hongrui Luo, Xinlei Chen, Xiaofei Wang, Hong Zhang 0009	26.3 A Closed-Loop Neuromodulation Chipset with 2-Level Classification Achieving 1.5Vpp CM Interference Tolerance, 35dB Stimulation Artifact Rejection in 0.5ms and 97.8% Sensitivity Seizure Detection.	ISSCC	2020	DBLP DOI BibTeX RDF
22	Jae-Sung An, Jong-Hyun Ra, Eunchul Kang, Michiel A. P. Pertijs, Sang-Hyun Han	28.1 A Capacitive Touch Chipset with 33.9dB Charge-Overflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation and Wireless Power and Data Transfer to an Active Stylus.	ISSCC	2020	DBLP DOI BibTeX RDF
22	Xin Wang, Yi Peng, Yuanxi Zhang, Tao Xia, Yifan Wu, Juncheng Wang, Lei Wang, Liujia Song, Lei Zhao, Shenglong Zhuo, Quan Pan 0002, Xuefeng Chen 0004, Patrick Yin Chiang, Rui Bai 0001	PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul.	OFC	2020	DBLP BibTeX RDF
22	Changjun Li, Zong-Shi Xie, Xin-Ran Peng, Bo Li 0072	Performance Evaluation and Improvement of Chipset Assembly & Test Production Line Based on Variability.	Int. J. Autom. Comput.	2019	DBLP DOI BibTeX RDF
22	Joanna Kolodziej, Horacio González-Vélez (eds.)	High-Performance Modelling and Simulation for Big Data Applications - Selected Results of the COST Action IC1406 cHiPSet		2019	DBLP DOI BibTeX RDF
22	Wooyoung Choi, Ivan Galkin, Seokwon Lee, Jihoon Park, Jongjin Lee, Dongyun Kim	Efficient NB-IoT and GNSS chipset solution.	ICECS	2019	DBLP DOI BibTeX RDF
22	Ye Xiao, Yi-Jun Zhu, Dongfang Zhang, Haiyong Zhang	High-Speed Visible Light Communication Chipset Based Multi-Color MIMO System.	WOCC	2019	DBLP DOI BibTeX RDF
22	Sanja Brdar, Olivera Novovic, Nastasija Grujic, Horacio González-Vélez, Ciprian-Octavian Truica, Siegfried Benkner, Enes Bajrovic, Apostolos Papadopoulos	Big Data Processing, Analysis and Applications in Mobile Cellular Networks.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Imen Rached, Elisabeth Larsson	Tail Distribution and Extreme Quantile Estimation Using Non-parametric Approaches.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Elisabeth Larsson, Afshin Zafari, Marco Righero, Matteo Alessandro Francavilla, Giorgio Giordanengo, Francesca Vipiana, Giuseppe Vecchi, Christoph W. Kessler, Corinne Ancourt, Clemens Grelck	Parallelization of Hierarchical Matrix Algorithms for Electromagnetic Scattering Problems.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Ales Zamuda, Vincenzo Crescimanna, Juan C. Burguillo, Joana Matos Dias, Katarzyna Wegrzyn-Wolska, Imen Rached, Horacio González-Vélez, Roman Senkerik, Claudia Pop, Tudor Cioara, Ioan Salomie, Andrea Bracciali	Forecasting Cryptocurrency Value by Sentiment Analysis: An HPC-Oriented Survey of the State-of-the-Art in the Cloud Era.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Catherine Maréchal, Dariusz Mikolajewski, Krzysztof Tyburek, Piotr Prokopowicz, Lamine Bougueroua, Corinne Ancourt, Katarzyna Wegrzyn-Wolska	Survey on AI-Based Multimodal Methods for Emotion Detection.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Irene Kilanioti, Alejandro Fernández-Montes, Damián Fernández-Cerero, Anthony Karageorgos, Christos Mettouris, Valentina Nejkovic, Nikolas Albanis, Rabih Bashroush, George A. Papadopoulos	Towards Efficient and Scalable Data-Intensive Content Delivery: State-of-the-Art, Issues and Challenges.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Valentina Nejkovic, Ari Visa, Milorad Tosic, Nenad Petrovic 0001, Mikko Valkama, Mike Koivisto, Jukka Talvitie, Svetozar Rancic, Daniel Grzonka, Jacek Tchórzewski, Pierre Kuonen, Francisco Gortázar	Big Data in 5G Distributed Applications.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Clemens Grelck, Ewa Niewiadomska-Szynkiewicz, Marco Aldinucci, Andrea Bracciali, Elisabeth Larsson	Why High-Performance Modelling and Simulation for Big Data Applications Matters.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Simone Spolaor, Marco Gribaudo, Mauro Iacono, Tomas Kadavy, Zuzana Komínková Oplatková, Giancarlo Mauri, Sabri Pllana, Roman Senkerik, Natalija Stojanovic, Esko Turunen, Adam Viktorin, Salvatore Vitabile, Ales Zamuda, Marco S. Nobile	Towards Human Cell Simulation.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Abdurrahman Olgaç, Asli Türe, Simla Olgaç, Steffen Möller	Cloud-Based High Throughput Virtual Screening in Novel Drug Discovery.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Salvatore Vitabile, Michal Marks, Dragan Stojanovic, Sabri Pllana, José Manuel Molina 0001, Mateusz Krzyszton, Andrzej Sikora, Andrzej Jarynowski, Farhoud Hosseinpour, Agnieszka Jakobik, Aleksandra Stojnev Ilic, Ana Respício, Dorin Moldovan, Cristina Pop 0001, Ioan Salomie	Medical Data Processing and Analysis for Remote Health and Activities Monitoring.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Joanna Kolodziej, Daniel Grzonka, Adrian Widlak, Pawel Kisielewicz	Ultra Wide Band Body Area Networks: Design and Integration with Computational Clouds.	High-Performance Modelling and Simulation for Big Data Applications	2019	DBLP DOI BibTeX RDF
22	Wooram Lee, Jean-Olivier Plouchart, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Scott K. Reynolds, Emre Apaydin, Alberto Valdes-Garcia	Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
22	Changjun Li, Bo Li 0072, Qiang Hu	Cycle time prediction and improvement of chipset assembly and test production line based on variability.	Prod. Eng.	2018	DBLP DOI BibTeX RDF
22	Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao 0004, Shuai Yuan 0005, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang 0001, Hanjun Jiang	A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
22	Andrea Bracciali, Elisabeth Larsson	Data-Intensive Modelling and Simulation in Life Sciences and Socio-economical and Physical Sciences - Contributions from the Coordinated Work in cHiPSet, the COST Action on High-Performance Modelling and Simulation for Big Data Applications.	Data Sci. Eng.	2017	DBLP DOI BibTeX RDF
22	Jingjing Dong, Hanjun Jiang, Kai Yang, Zhaoyang Weng, Fule Li, Jianjun Wei, Yanqing Ning, Xinkai Chen, Zhihua Wang 0001	A Wireless Body Sound Sensor with a Dedicated Compact Chipset.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
22	Anirban Sengupta, Dipanjan Roy	Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].	IEEE Consumer Electron. Mag.	2017	DBLP DOI BibTeX RDF
22	Muyiwa Joshua Adeleke, Andreas Grebe, Mathias Kretschmer, Jens Mödeker	Spectrum Utilization Assessment of Wi-Fi Network Using Qualcomm/Atheros 802.11 Wireless Chipset.	AFRICOMM	2017	DBLP DOI BibTeX RDF
22	Frank Y. Chang, Yi Sun, Robert Lingle, You Zhang, Pengfei Cai, Mengyuan Huang, Dong Pan, Timo Gray, Sudeep Bhoja, Stephen Nelson, Jim Tatum	First demonstration of PAM4 transmissions for record reach and high-capacity SWDM links over MMF using 40G/100G PAM4 IC chipset with real-time DSP.	OFC	2017	DBLP BibTeX RDF
22	Shuai Yuan 0005, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang 0001	A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
22	Frank Y. Chang, Sudeep Bhoja, Jamal Riani, Ishwar Hosagrahar, Jennifer Wu, Sameer Herlekar, Arun Tiruvur, Pulkit Khandelwal, Karthik Gopalakrishnan	Link performance investigation of industry first 100G PAM4 IC chipset with real-time DSP for data center connectivity.	OFC	2016	DBLP BibTeX RDF
22	Ke Huang 0003, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang 0001	A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.	CICC	2015	DBLP DOI BibTeX RDF
22	Xiaodong Deng, Yihu Li, Wen Wu, Yong-Zhong Xiong	D-band down conversion chipset with I-Q outputs using 0.13μm SiGe BiCMOS technology.	ASICON	2015	DBLP DOI BibTeX RDF
22	Michael Boers, Bagher Afshar, Iason Vassiliou, Saikat Sarkar 0001, Sean T. Nicolson, Ehsan Adabi, Bevin George Perumana, Theodoros Chalvatzis, Spyros Kavvadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Jesus A. Castaneda, Tirdad Sowlati, Maryam Rofougaran, Ahmadreza Rofougaran	A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
22	Mizuki Motoyoshi, Naoko Ono, Kosuke Katayama, Kyoya Takano, Minoru Fujishima	135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
22	Michael Boers, Iason Vassiliou, Saikat Sarkar 0001, Sean T. Nicolson, Ehsan Adabi, Bagher Afshar, Bevin G. Perumana, Theodoros Chalvatzis, Spyros Kavadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Namik Kocaman, Adesh Garg, Hans Eberhart, Phil Yang, Hongyu Xie, Hea Joung Kim, Alireza Tarighat Mehrabani, David Garrett, Andrew J. Blanksby, Mong Kuan Wong, Durai Pandian Thirupathi, Siukai Mak, Radha Srinivasan, Amir Ibrahim, Ersin Sengul, Vincent Roussel, Po-Chao Huang, Tsuifang Yeh, Murat Mese, Jesus A. Castaneda, Brima Ibrahim, Tirdad Sowlati, Maryam Rofougaran, Ahmadreza Rofougaran	20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity.	ISSCC	2014	DBLP DOI BibTeX RDF
22	Shuichi Nagai, Yasuhiro Yamada, Noboru Negoro, Hiroyuki Handa, Yuji Kudoh, Hiroaki Ueno, Masahiro Ishida, Nobuyuki Otuska, Daisuke Ueda	30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies.	ISSCC	2014	DBLP DOI BibTeX RDF
22	Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto	98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao 0001	A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang 0018, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa	Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Shahriar Shahramian, Yves Baeyens, Noriaki Kaneda, Young-Kai Chen	A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Noriaki Saito, Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shirakawa, Naoya Yosoku, Akira Yamamoto, Ryosuke Shiozaki, Koji Takinami	A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
22	Fabio Pisoni, Philip G. Mattos	A BeiDou hardware receiver based on the STA8088 chipset.	ICL-GNSS	2013	DBLP DOI BibTeX RDF
22	Johan H. C. van den Heuvel, Hans W. Pflug, A. Ramkumar, Alex Young, Jac Romme, Martijn Hijdra, Benjamin Busze, Arjan Breeschoten, Gerard J. M. Janssen, Guido Dolmans, Kathleen Philips, Harmke de Groot	Real time non-coherent synchronization method in 6-10.6 GHz IR-UWB demonstrator chipset.	GLOBECOM	2013	DBLP DOI BibTeX RDF
22	Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shirakawa, Naoya Yosoku, Akira Yamamoto, Ryosuke Shiozaki, Noriaki Saito	A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Steven Brebels, Wim Van Thillo, Kristof Vaesen, Bertrand Parvais, Vadim Issakov, Mike Libois, Michiaki Matsuo, John R. Long, Charlotte Soens, Piet Wambacq	A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao 0001	A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Marc Tiebout, Hans-Dieter Wohlmuth, Herbert Knapp, Raffaele Salerno, Michael Druml, Mirjana Rest, Johann Kaeferboeck, Johann Wuertele, Sherif Sayed Ahmed, Andreas Schiessl, Ralf Juenemann, Anna Zielska	Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
22	Sanming Hu, Yong-Zhong Xiong, Bo Zhang, Lei Wang, Teck-Guan Lim, Minkyu Je, Mohammad Madihian	A SiGe BiCMOS Transmitter/Receiver Chipset With On-Chip SIW Antennas for Terahertz Applications.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
22	Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang 0018, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa	A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
22	Shyuan Liao, Yen-Shuo Chang, Chia-Hsin Wu, Hung-Chieh Tsai, Hsin-Hua Chen, Min Chen, Ching-Wen Hsueh, Jian-Bang Lin, Den-Kai Juang, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chih-Heng Shih, Barry Hong, Heng-Ruey Hsu, Chih-Yuan Wang, Meng-Shiang Lin, Wei-Hsiang Tseng, Che-Hsiung Yang, Lawrence Chen Lee, Ting-Jyun Jheng, Wen-Wei Yang, Ming-Yang Chao, Jyh-Shin Pan	A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
22	Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali 0001, Nick Huang, Bo Zhang 0029, Afshin Momtaz, Jun Cao 0001	A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
22	Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima	A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
22	Jun Zhou 0008, Didem Unat, Dong Ju Choi, Clark C. Guest, Yifeng Cui	Hands-on Performance Tuning of 3D Finite Difference Earthquake Simulation on GPU Fermi Chipset.	ICCS	2012	DBLP DOI BibTeX RDF
22	Oded Katz, Roee Ben Yishay, Roi Carmon, Benny Sheinman, Frank Szenher, Donald Papae, Danny Elad	A fully integrated SiGe E-BAND transceiver chipset for broadband point-to-point communication.	RWS	2012	DBLP DOI BibTeX RDF
22	Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang 0018, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa	A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer A. Ali 0001, Nick Huang, Wei Zhang, Bo Zhang 0029, Afshin Momtaz, Jun Cao 0001	A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Xiaoyan Wang 0002, Yikun Yu, Benjamin Busze, Hans W. Pflug, Alex Young, Xiongchuan Huang, Cui Zhou, Mario Konijnenburg, Kathleen Philips, Harmke de Groot	A meter-range UWB transceiver chipset for around-the-head audio streaming.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima	135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF