|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 239 occurrences of 145 keywords
|
|
|
Results
Found 319 publication records. Showing 319 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
132 | Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed |
A new paradigm for synthesis and propagation of clock gating conditions. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
low-power design, clock gating |
120 | Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron |
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
architecture, power, temperature, clock gating |
114 | Eli Arbel, Cindy Eisner, Oleg Rokhlenko |
Resurrecting infeasible clock-gating functions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
clustering, low power, approximation, clock gating |
113 | Vishwanadh Tirumalashetty, Hamid Mahmoodi |
Clock Gating and Negative Edge Triggering for Energy Recovery Clock. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
109 | Nainesh Agarwal, Nikitas J. Dimopoulos |
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
105 | Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler |
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
105 | Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero |
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
105 | Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
104 | Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001 |
Improve clock gating through power-optimal enable function selection. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
101 | Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel |
Power-Clock Gating in Adiabatic Logic Circuits. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
93 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Gate planning during placement for gated clock network. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
90 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
low power, ASIP, clock gating, VLIW processor |
90 | Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu |
Logic synthesis for low power using clock gating and rewiring. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
low power, logic synthesis, clock gating |
90 | Hans M. Jacobson |
Improved clock-gating through transparent pipelining. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating |
87 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija |
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis |
85 | Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii |
Clock-tree power optimization based on RTL clock-gating. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
clock-tree synthsis, low-power design |
85 | Fei Li 0003, Lei He 0001 |
Maximum current estimation considering power gating. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
low-power design, ATPG, power estimation, power gating |
83 | Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
82 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Efficient Automated Clock Gating Using CoDeL. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
81 | Chunhong Chen, Changjun Kang, Majid Sarrafzadeh |
Activity-sensitive clock tree construction for low power. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
low power, clock gating, clock tree, activity pattern |
80 | Nithya Raghavan, Venkatesh Akella, Smita Bakshi |
Automatic Insertion of Gated Clocks at Register Transfer Level. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
80 | Ashutosh Chakraborty, David Z. Pan |
Skew management of NBTI impacted gated clock trees. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
clock skew, clock gating, NBTI |
78 | Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang |
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
78 | Yan Zhang, Jussi Roivainen, Aarne Mämmelä |
Clock-Gating in FPGAs: A Novel and Comparative Evaluation. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
72 | Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang |
A novel sequential circuit optimization with clock gating logic. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
72 | Aaron P. Hurst |
Automatic synthesis of clock gating logic with controlled netlist perturbation. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
low power, clock gating, logic optimization, dynamic power |
69 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity and register placement aware gated clock network design. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
gated clock tree, low power, placement |
68 | Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri |
A novel clock distribution and dynamic de-skewing methodology. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
68 | Li Li, Ken Choi, Seongmo Park, MooKyung Chung |
Selective clock gating by using wasting toggle rate. |
EIT |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Martin Saint-Laurent, Animesh Datta |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
clock gater, clock gating cell, local clock buffer, set-reset latch |
65 | Monica Donno, Enrico Macii, Luca Mazzoni |
Power-aware clock tree planning. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
clock tree synthesis and routing, physical design and optimization, low-power design, digital design |
64 | Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao |
Clock gating effectiveness metrics: Applications to power optimization. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
59 | Nilanjan Banerjee, Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Swarup Bhunia |
Low power synthesis of dynamic logic circuits using fine-grained clock gating. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
59 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
55 | Pietro Babighian, Luca Benini, Enrico Macii |
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances |
55 | Wael El-Essawy, David H. Albonesi, Balaram Sinharoy |
A microarchitectural-level step-power analysis tool. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise |
55 | Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, T. N. Vijaykumar, Kaushik Roy 0001 |
Deterministic Clock Gating for Microprocessor Power Reduction. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
|
51 | Jun Seomun, Insup Shin, Youngsoo Shin |
Synthesis and implementation of active mode power gating circuits. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
active leakage, active-mode power gating, low power |
51 | Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat |
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng |
Predicting the worst-case voltage violation in a 3D power network. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
worst case violation prediction, integer linear programming, leakage, clock gating, power networks |
50 | Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi 0001, Takayasu Sakurai |
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Power efficient rapid hardware development using CoDel and automated clock gating. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Xunwei Wu, Massoud Pedram |
Low power sequential circuit design by using priority encoding and clock gating. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
50 | Jens Brandt 0001, Klaus Schneider 0001, Sumit Ahuja, Sandeep K. Shukla |
The Model Checking View to Clock Gating and Operand Isolation. |
ACSD |
2010 |
DBLP DOI BibTeX RDF |
operand isolation, model checking, clock gating |
50 | Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori |
Low-Power Design of 90-nm SuperH Processor Core. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
48 | Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou |
Energy Recovering ASIC Design. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
47 | Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang |
Power Consumption Analysis of Embedded Multimedia Application. |
ICESS |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Amar A. Rasheed, Hacer Varol, Mohamed Baza |
Clock Gating-Assisted Malware (CGAM): Leveraging Clock Gating On ARM Cortex M* For Attacking Subsystems Availability. |
ISDFS |
2021 |
DBLP DOI BibTeX RDF |
|
45 | Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich |
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Eric L. Hill, Mikko H. Lipasti |
Stall cycle redistribution in a transparent fetch pipeline. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
pipeline gating, microarchitecture, dynamic power, instruction fetch |
45 | Yan Luo, Jia Yu 0008, Jun Yang 0002, Laxmi N. Bhuyan |
Conserving network processor power consumption by exploiting traffic variability. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
scheduling, low power, Network processor, clock gating |
42 | Ramkumar Jayaseelan, Tulika Mitra |
Dynamic thermal management via architectural adaptation. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
architecture adaptation, dynamic thermal management |
41 | M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-Moneum, Mark M. Tehranipoor |
O'clock: lock the clock via clock-gating for SoC IP protection. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
41 | Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen |
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Low power, ASIP, ECG, Clock gating, Wireless sensor node |
41 | Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin |
Speculative software management of datapath-width for energy optimization. |
LCTES |
2004 |
DBLP DOI BibTeX RDF |
narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating |
41 | Juanjo Noguera, Rosa M. Badia |
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs |
41 | Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster |
Synchronous Interlocked Pipelines. |
ASYNC |
2002 |
DBLP DOI BibTeX RDF |
progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked |
39 | Arjun Rajagopal |
Clock tree design challenges for robust and low power design. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
NBTI, IR drop |
39 | Jindrich Zejda, Paul Frain |
General framework for removal of clock network pessimism. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron |
37 | Wanping Zhang, Yi Zhu 0002, Wenjian Yu, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng |
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki |
An automated runtime power-gating scheme. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
37 | David M. Brooks, Margaret Martonosi |
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. |
ACM Trans. Comput. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Songyao Tan, Yue Yin, Hanjun Jiang, Zhihua Wang 0001 |
A 0.7-V Clock-gating Cell with Power Gating Technology and 1.56-pA Sleep Power. |
ICTA |
2020 |
DBLP DOI BibTeX RDF |
|
37 | Li Li, Ken Choi, Haiqing Nan |
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. |
IEEE Trans. Very Large Scale Integr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
37 | Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
37 | Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin |
Pulser gating: A clock gating of pulsed-latch circuits. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
37 | Li Li, Ken Choi, Haiqing Nan |
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
35 | Aida Todri, Malgorzata Marek-Sadowska |
A study of reliability issues in clock distribution networks. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero |
Clock gate on abort: Towards energy-efficient hardware Transactional Memory. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Jae-Gon Lee, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin |
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. |
IEEE J. Solid State Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim |
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
32 | Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu |
Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2016 |
DBLP DOI BibTeX RDF |
|
32 | Jianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan |
Clock domain crossing aware sequential clock gating. |
DATE |
2015 |
DBLP BibTeX RDF |
|
32 | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
Co-synthesis of data paths and clock control paths for minimum-period clock gating. |
DATE |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Hoi-Jin Lee, Jong-Woo Kim, Tae Hee Han, Jae-Cheol Son, Jeong-Taek Kong, Bai-Sun Kong |
Low-power dual-supply clock networks with clock gating and frequency doubling. |
IEICE Electron. Express |
2012 |
DBLP DOI BibTeX RDF |
|
32 | Shih-Hsu Huang, Chia-Ming Chang 0002, Wen-Pin Tu, Song-Bin Pan |
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
32 | Roni Wiener, Gila Kamhi, Moshe Y. Vardi |
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
32 | José C. Monteiro 0001, Arlindo L. Oliveira |
Implicit FSM decomposition applied to low-power design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
32 | José C. Monteiro 0001, Arlindo L. Oliveira |
Finite State Machine Decomposition For Low Power. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
system-on-chip test, testing embedded core, intellectual property test |
31 | Gustavo R. Wilke, Rajeev Murgai |
Design and Analysis of "Tree+Local Meshes" Clock Architecture. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi |
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt |
System level power estimation methodology with H.264 decoder prediction IP case study. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
42% power savings through glitch-reducing clocking strategy in a hearing aid application. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Howard Chen 0001, Daniel L. Ostapko |
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Wai-Kwong Lee, Chi-Ying Tsui |
Finite state machine partitioning for low power. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla |
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction |
27 | P. Subramanian, Jagonda Patil, Manish Kumar Saxena |
FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications. |
IWCMC |
2009 |
DBLP DOI BibTeX RDF |
ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating |
27 | Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell, Vineet Chadha, Jaideep Moses |
Rate-based QoS techniques for cache/memory in CMP platforms. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs |
27 | Wei-Chung Chao, Wai-Kei Mak |
Low-power gated and buffered clock network construction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
low power, buffer, clock gating, Clock tree, zero-skew |
27 | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
Power-efficient LDPC code decoder architecture. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
FIFO buffer, LDPC decoder, intermediate message compression technique, message-passing schedule, clock gating |
27 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau |
Aggregating processor free time for energy reduction. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction |
27 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz |
Experimental measurement of a novel power gating structure with intermediate power saving mode. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
27 | Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson |
Design and implementation of the POWER5 microprocessor. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor |
27 | Sandeep Kumar Goel, Bart Vermeulen |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains |
27 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel |
Understanding and minimizing ground bounce during mode transition of power gating structures. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
27 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
Displaying result #1 - #100 of 319 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ >>] |
|