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Publication years (Num. hits)
1995-2011 (15) 2013-2019 (5)
Publication types (Num. hits)
article(8) inproceedings(12)
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Found 20 publication records. Showing 20 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
161Jae-Joon Kim, Kaushik Roy 0001 A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
103Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. Search on Bibsonomy IWSOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Sepideh Valiollahi, Gholamreza Ardeshir An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all-digital time-based quantization. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
34Weiwei Ge, Lijuan Han, Yuan Cao 0003, Enyi Yao, Xiaojin Zhao A Novel Low Voltage DCVSL Circuit Design based on Wilson Current Mirror. Search on Bibsonomy APCCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
34Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda On Improving the Performance of Dynamic DCVSL Circuits. Search on Bibsonomy J. Electr. Comput. Eng. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
34Hadar Dagan, Adam Teman, Evgeny Pikhay, Vladislav Dayan, Anatoli Mordakhay, Yakov Roizin, Alexander Fish A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
34Ho Joon Lee, Yong-Bin Kim Low power Null Convention Logic circuit design based on DCVSL. Search on Bibsonomy MWSCAS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
34Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34José F. da Rocha, Marcelino Bicho Dos Santos, José M. Dores Costa, Floriberto A. Lima Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter. Search on Bibsonomy IEEE Trans. Ind. Electron. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada Pre-conditioning Free Footless DCVSL for High-performance Datapaths. Search on Bibsonomy ICECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Xunwei Wu, Guoqiang Hang, Massoud Pedram Low power DCVSL circuits employing AC power supply. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dcvsl, high speed digital, pipeline, error detect, soft error
33Parag K. Lala, Anup Singh, Alvernon Walker A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
23Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda Measurement of power supply noise tolerance of self-timed processor. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun Design for Self-Checking and Self-Timed Datapath. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits
23Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun A Totally Self-Checking Dynamic Asynchronous Datapath. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider
23Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23Madhuban Kishor, José Pineda de Gyvez Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi An Asynchronous Morphological Processor for Multi-Media Applications. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
23Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry Differential BiCMOS logic circuits: fault characterization and design-for-testability. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
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