Search results for "decoders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Kuang Yung Liu	Architecture for VLSI Design of Reed-Solomon Decoders.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	BCH decoders, finite field processors, Reed?Solomon decoders, parallel processing, VLSI, error-correcting codes, pipeline processing
59	Ahmad A. Hiasat	VLSI implementation of new arithmetic residue to binary decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
56	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	Computational Graceful Degradation for Video Sequence Decoding.	ICIP (1)	1997	DBLP DOI BibTeX RDF	computational graceful degradation, video sequence decoding, software based video decoders, dedicated hardware real time systems, video/audio decoders, video compression standards, video/audio bitstreams processing, multimedia processors, compressed video sequences, H.263 video compression standard, video processor platform, interfaces, video coding, simulation results, real-time performance, main memory, IDCT, hardware platform
55	Aggelos Kiayias, Moti Yung	On Crafty Pirates and Foxy Tracers.	Digital Rights Management Workshop	2001	DBLP DOI BibTeX RDF
50	Alina Maor, Neri Merhav	On Successive Refinement With Causal Side Information at the Decoders.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
50	Matthew Collin Jordan, Ramachandran Vaidyanathan	Configurable decoders with application in fast partial reconfiguration of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, decoder, look-up table, configurable logic
50	Duong Hieu Phan	Traitor Tracing for Stateful Pirate Decoders with Constant Ciphertext Rate.	VIETCRYPT	2006	DBLP DOI BibTeX RDF
50	Wei Qin, Sharad Malik	Automated synthesis of efficient binary decoders for retargetable software toolkits.	DAC	2003	DBLP DOI BibTeX RDF	binary decoder, decoding tree, decision tree, instruction set simulator
50	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002	Memory arrangements in turbo decoders using sliding-window BCJR algorithm.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
50	Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi	Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	adaptive decoding, MAP algorithm, VLSI implementation, turbo codes
50	Emil Gizdarski	Detection of Delay Faults in Memory Address Decoders.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	Built-In Self-Test, delay testing, stuck-open faults, RAM testing
46	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	address decoders, memory testing, dynamic faults
46	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
41	Min Li 0001, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor	An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.	SiPS	2008	DBLP DOI BibTeX RDF
41	Zhihang Yi, Il-Min Kim	Joint optimization of relay-precoders and decoders with partial channel side information in cooperative networks.	IEEE J. Sel. Areas Commun.	2007	DBLP DOI BibTeX RDF
41	Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Friedbert Berens, Andreas Ruegg	A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems.	VTC Spring	2007	DBLP DOI BibTeX RDF
41	Ying Zhao, Yang Xiao	A design of orthogonal interleavers for multimodes turbo en-decoders.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
41	Mohammad M. Mansour, Naresh R. Shanbhag	VLSI architectures for SISO-APP decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
41	Felix Lustenberger, Hans-Andrea Loeliger	On mismatch errors in analog-VLSI error correcting decoders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
37	Khalid A. Darabkh, Backer N. Abu-Jaradeh	Bounded Fano Decoders over Intermediate Hops Excluding Packet Retransmission.	AINA	2010	DBLP DOI BibTeX RDF	Fano decoders, upper and lower threshold limits, Pareto distribution and average queue size
37	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak	Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Reed-Solomon decoders, Sudan's algorithm, Guruswami-Sudan algorithm, Koetter-Vardy algorithm, Hasse derivative, VLSI architectures, list decoding, polynomial interpolation, soft-decision decoding
37	Matthias Klaus, Ad J. van de Goor	Tests for Resistive and Capacitive Defects in Address Decoders.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling
36	Narayan Prasad, Inaki Berenguer, Xiaodong Wang 0001	Design of Spherical Lattice Space-Time Codes.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
36	Arul D. Murugan, Hesham El Gamal, Mohamed Oussama Damen, Giuseppe Caire	A unified framework for tree search decoding: rediscovering the sequential decoder.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
36	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	Area-efficient high-throughput MAP decoder architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
36	Haruhiko Kaneko	Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment.	DFT	2005	DBLP DOI BibTeX RDF
36	Juan A. Garay, Jessica Staddon, Avishai Wool	Long-Lived Broadcast Encryption.	CRYPTO	2000	DBLP DOI BibTeX RDF
36	Moni Naor, Benny Pinkas	Threshold Traitor Tracing.	CRYPTO	1998	DBLP DOI BibTeX RDF
33	Liang-Jin Lin, Antonio Ortega	Perceptually Based Video Rate Control Using Pre-Filtering and Predicted Rate-Distortion Characteristics.	ICIP (2)	1997	DBLP DOI BibTeX RDF	perceptually based video rate control, predicted rate-distortion characteristics, digital video coding, output data rate, output quality, MPEG Test Model 5, channel rates, video sources, block classification, rate control optimization process, MPEG decoders, H.263 encoders, MPEG-4 encoders, blockiness, rate distortion theory, pre-filtering, MPEG-1, computational overhead
33	Daby M. Sow, Alexandros Eleftheriadis	Algorithmic Representation of Visual Information.	ICIP (2)	1997	DBLP DOI BibTeX RDF	algorithmic representation, complexity distortion theory, programmable communication systems design, programmable decoders, intelligent encoders design, tools downloading, audio-visual information, video coding, MPEG-4, rate distortion theory, visual information, algorithm selection
33	Heng Liao, Andrew Wolfe	Available Parallelism in Video Applications.	MICRO	1997	DBLP DOI BibTeX RDF	MPEG1, MPEG2, SPEC benchmarks, audio applications, general-purpose applications, linear complexity global scheduling algorithm, video coding, encoders, instruction-level parallelism, decoders, optimization techniques, MPEG4, H.263, media processors, video applications, graphics applications
31	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Daesun Oh, Keshab K. Parhi	Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Michael A. Turi, José G. Delgado-Frias	High-performance low-power AND and Sense-Amp address decoders with selective precharging.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Zhongfeng Wang 0001	High-Speed Recursion Architectures for MAP-Based Turbo Decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
31	Frédéric Guilloud, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger	Generic Description and Synthesis of LDPC Decoders.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
31	Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu	Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders.	ISCAS	2007	DBLP DOI BibTeX RDF
31	Jia Wang 0003, Ming-Yang Kao, Hai Zhou 0001	Address generation for nanowire decoders.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	testing, decoder, nanowire
31	Khalid A. Darabkh, W. David Pan	Stationary queue-size distribution for variable complexity sequential decoders with large timeout.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	Fano decoder, queue size distribution, timeout
31	Shantanu Chakrabartty	CMOS analog iterative decoders using margin propagation circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Yin-Tsung Hwang, Jun-Hong Chen	VLSI architectural design tradeoffs for sliding-window log-MAP decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
31	Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier, Norbert Wehn	A Scalable System Architecture for High-Throughput Turbo-Decoders.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	wireless, VLSI architectures, interleaving, high-throughput, Turbo-Decoder, parallel decoding
31	Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel	Digital built-in self-test of CMOS analog iterative decoders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
31	Christian Neeb, Michael J. Thul, Norbert Wehn	Network-on-chip-centric approach to interleaving in high throughput channel decoders.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
31	Jun Jin Kong, Keshab K. Parhi	Low-latency architectures for high-throughput rate Viterbi decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
31	Mohamed Azimane, Ananta K. Majhi	New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders.	VTS	2004	DBLP DOI BibTeX RDF
31	Mohammad M. Mansour, Naresh R. Shanbhag	High-throughput LDPC decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
31	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
31	Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel	Cell library for automatic synthesis of analog error control decoders.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
31	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Ming-Hwa Sheu	VLSI architecture of extended in-place path metric update for Viterbi decoders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
31	Chaitali Chakrabarti, Clint Mumford	Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
31	Mariana-Eugenia Petre, Guido Masera	A Parametrical Architecture for Reed-Solomon Decoders.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
27	Eirik Rosnes	Stopping Set Analysis of Iterative Row-Column Decoding of Product Codes.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
27	Soheil Mohajer, Chao Tian 0002, Suhas N. Diggavi	Asymmetric Multi-level Diversity Coding.	DCC	2008	DBLP DOI BibTeX RDF
27	Yuanliang Huang, Jiangzhou Wang, Kenichi Higuchi	A Novel Layered Space-Time-Frequency Architecture with Convolutional Coding.	VTC Spring	2007	DBLP DOI BibTeX RDF
27	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Aggelos Kiayias, Serdar Pehlivanoglu	Pirate Evolution: How to Make the Most of Your Traitor Keys.	CRYPTO	2007	DBLP DOI BibTeX RDF
27	Nima Sadeghi, Sheryl L. Howard, Soraya Kasnavi, Kris Iniewski, Vincent C. Gaudet, Christian Schlegel	Analysis of error control code use in ultra-low-power wireless sensor networks.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Fei Sun, Tong Zhang 0002	Parallel high-throughput limited search trellis decoder VLSI design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Todd P. Coleman, Muriel Médard, Michelle Effros	Towards Practical Minimum-Entropy Universal Decoding.	DCC	2005	DBLP DOI BibTeX RDF
27	Michael J. Thul, Norbert Wehn, L. P. Rao	Enabling high-speed turbo-decoding through concurrent interleaving.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
27	Gerald W. Neufeld, Yueli Yang	The Design and Implementation of an ASN.1-C Compiler.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	abstract syntax notation one, ASN.1-C compiler, international standard specification, transfer-syntax, basic encoding rules, external data representation, ED library, CASN1, design, user interface, protocol, protocols, standards, C, implementation, encoding, program compilers, decoding, decoding
26	Aleksander Kubica, Nicolas Delfosse	Efficient color code decoders in d≥2 dimensions from toric code decoders.	Quantum	2023	DBLP DOI BibTeX RDF
26	Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg	Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.	CoRR	2017	DBLP BibTeX RDF
26	Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg	Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.	WCNC Workshops	2017	DBLP DOI BibTeX RDF
26	Alexios Balatsoukas-Stimming	Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders.		2016	DOI RDF
26	Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross	Unrolled Polar Decoders, Part II: Fast List Decoders.	CoRR	2015	DBLP BibTeX RDF
26	Matthew Collin Jordan, Ramachandran Vaidyanathan	MU-decoders: A class of fast and efficient configurable decoders.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
23	Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
23	Ziad Al Kachouh, Maurice G. Bellanger	Exact DCT-Based Spatial Domain Interpolation of Blocks in Images.	ICIP (1)	1997	DBLP DOI BibTeX RDF	exact DCT-based spatial domain interpolation, image blocks, image decoders, simulations, image processing, image coding, image coding, image restoration, pixels, computation cost
23	Manoj Franklin, Kewal K. Saluja	Hypergraph Coloring and Reconfigured RAM Testing.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
23	Tsutomu Sasao	On the Optimal Design of Multiple-Valued PLA's.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	multiple-valued PLAs, literal functions, 2-bit decoders, logic design, programmable logic arrays, many-valued logics, optimal design, logic arrays, permutation network
22	Osamu Shimada, Toshiyuki Nomura, Akihiko Sugiyama, Masahiro Serizawa	Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Audio codec, 3GPP enhanced aacPlus, DSP implementation, Memory size, Computational complexity, Tradeoff
22	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez	Parallel Scalability of Video Decoders.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
22	Xinming Huang 0001, Cao Liang, Jing Ma 0006	System Architecture and Implementation of MIMO Sphere Decoders on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Chuanjun Zhang	Reducing cache misses through programmable decoders.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	low power, Cache, dynamic optimization
22	Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt	Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking
22	Maximilien Gadouleau, Zhiyuan Yan 0001	On the Decoder Error Probability of Bounded Rank-Distance Decoders for Maximum RankDistance Codes.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
22	Narayan Prasad, Mahesh K. Varanasi, Luca Venturino, Xiaodong Wang 0001	An Analysis of the MIMO-SDMA Channel With Space-Time Orthogonal and Quasi-Orthogonal User Transmissions and Efficient Successive Cancellation Decoders.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
22	Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross	Fully Parallel Stochastic LDPC Decoders.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
22	Renfei Liu, Keshab K. Parhi	Minimal complexity low-latency architectures for Viterbi decoders.	SiPS	2008	DBLP DOI BibTeX RDF
22	Rafal Dlugosz, Vincent C. Gaudet	Current-mode memory cell with power down phase for discrete time analog iterative decoders.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Mahdi Shabany, P. Glenn Gulak	Scalable VLSI architecture for K-best lattice decoders.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri	High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	code construction, fully-parallel VLSI implementation, network of PLAs, iterative decoding, low-density parity-check codes
22	Saied Hemati, Amir H. Banihashemi	Convergence Speed and Throughput of Analog Decoders.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
22	Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci	Low complexity LDPC code decoders for next generation standards.	DATE	2007	DBLP DOI BibTeX RDF
22	Zhengya Zhang, Lara Dolecek, Martin J. Wainwright, Venkat Anantharam, Borivoje Nikolic	Quantization Effects in Low-Density Parity-Check Decoders.	ICC	2007	DBLP DOI BibTeX RDF
22	Soo-Woong Lee, B. V. K. Vijaya Kumar	Application of Soft-Decision Decoders to Non Narrow-Sense Reed-Solomon Codes.	ICC	2007	DBLP DOI BibTeX RDF
22	Christian Spagnol, William P. Marnane, Emanuel M. Popovici	FPGA Implementations of LDPC over GF(2m) Decoders.	SiPS	2007	DBLP DOI BibTeX RDF
22	Rachit Agarwal 0001, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko	A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Yang Liu 0016, Tong Zhang 0002, Jiang Hu	Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.	ISQED	2007	DBLP DOI BibTeX RDF
22	Benjamin Farber, Kenneth Zeger	Quantizers with uniform decoders and channel-optimized encoders.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
22	Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel	A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.	ISVLSI	2006	DBLP DOI BibTeX RDF
22	Chen Sun, Makoto Taromaru, Nemai Chandra Karmakar	On the Combination of Receive Beamforming with Alamouti Decoders.	VTC Spring	2006	DBLP DOI BibTeX RDF
22	Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera	Interconnection framework for high-throughput, flexible LDPC decoders.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
22	Yuping Zhang, Jun Tang, Keshab K. Parhi	Low Complexity List Updating Circuits for List Sphere Decoders.	SiPS	2006	DBLP DOI BibTeX RDF
22	Eric Rachlin, John E. Savage	Nanowire addressing with randomized-contact decoders.	ICCAD	2006	DBLP DOI BibTeX RDF
22	Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang	Efficient path metric access for reducing interconnect overhead in Viterbi decoders.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec	The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.	HICSS	2006	DBLP DOI BibTeX RDF