Search results for "defect-tolerant"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Nobuhiro Tomabechi	Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems.	DFT	1999	DBLP DOI BibTeX RDF	subsystem-dividing, yield, defect-tolerant, WSI, multi-dimensional
66	Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao	Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core.	DFT	2000	DBLP DOI BibTeX RDF
62	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.	DFT	2006	DBLP DOI BibTeX RDF	defective interconnects, defect’s severity, fault model, crosstalk, bridging fault
59	Mehdi Baradaran Tahoori	Application-independent defect-tolerant crossbar nano-architectures.	ICCAD	2006	DBLP DOI BibTeX RDF
58	Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.	VLSI Design	2008	DBLP DOI BibTeX RDF
57	Vijay K. Jain, Glenn H. Chapman	Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.	DFT	2006	DBLP DOI BibTeX RDF	3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance
57	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
57	Claude Thibeault, Yvon Savaria, Jean-Louis Houle	Test quality of hierarchical defect-tolerant integrated circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	defect level, fault coverage, defect tolerance, defect modeling, Combinatorial analysis
50	V. Hecht, Karsten Rönner, Peter Pirsch	A defect-tolerant systolic array implementation for real time image processing.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
49	Mehdi Baradaran Tahoori	Application-independent defect tolerance of reconfigurable nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
48	Debayan Bhaduri, Sandeep K. Shukla	NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CTMR, defect-tolerant architecture, nanotechnology, granularity, TMR, PRISM
46	Konstantin Likharev	Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
44	Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck	A self-organizing defect tolerant SIMD architecture.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
44	Hayssam El-Razouk, Zine Abid	A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits.	CCECE	2006	DBLP DOI BibTeX RDF
44	Gethin Norman, David Parker 0001, Marta Z. Kwiatkowska, Sandeep K. Shukla	Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking.	VLSI Design	2004	DBLP DOI BibTeX RDF
43	Mehdi Baradaran Tahoori	Low-overhead defect tolerance in crossbar nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
43	Rahul Jain 0004, Anindita Mukherjee, Kolin Paul	Defect-Aware Design Paradigm for Reconfigurable Architectures.	ISVLSI	2006	DBLP DOI BibTeX RDF
41	Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki	Transistor-level based defect tolerance for reliable nanoelectronics.	AICCSA	2008	DBLP DOI BibTeX RDF
41	Tao Xu 0002, Krishnendu Chakrabarty, Fei Su	Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips.	VLSI Design	2007	DBLP DOI BibTeX RDF
39	Gang Wang 0015, Wenrui Gong, Ryan Kastner	Defect-Tolerant Nanocomputing Using Bloom Filters.	FCCM	2006	DBLP DOI BibTeX RDF
38	Debayan Bhaduri, Sandeep K. Shukla	NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures.	ISVLSI	2004	DBLP DOI BibTeX RDF
38	Fred J. Meyer, Nohpill Park	Predicting Defect-Tolerant Yield in the Embedded Core Context.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Yield, integrated circuit, defect tolerance, embedded core
36	Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro	Reliability aware yield improvement technique for nanotechnology based circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	reliability, nanotechnology, yield improvement
36	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
36	Claude Thibeault, Yvon Savaria, Jean-Louis Houle	A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	defect-tolerant integrated circuits, optimum number of spares, reconfiguration strategies, optimum redundancy, VLSI, logic testing, redundancy, defect tolerance, circuit reliability, yield models, integrated circuit manufacture
36	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
35	Mehdi Baradaran Tahoori	BISM: built-in self map for hybrid crossbar nano-architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crossbar array, emerging nanotechnologies, logic mapping
35	Arvind Kumar, Sandip Tiwari	Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics.	DFT	2004	DBLP DOI BibTeX RDF
33	Marco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini	Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis.	DFT	1998	DBLP DOI BibTeX RDF	Slice, Defect Tolerance, Data-Path
33	Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth	A Defect-Tolerant and Fully Testable PLA.	DAC	1988	DBLP BibTeX RDF
30	Masaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi	An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	DNA self-assembled networks, Defect isolation, 1-hop wave expansion, Unsafe node detection, Gross defect model, Broadcast
30	Mehdi Baradaran Tahoori	Defects, Yield, and Design in Sublithographic Nano-electronics.	DFT	2005	DBLP DOI BibTeX RDF
28	Arvind Kumar, Sandip Tiwari	Defect tolerance for nanocomputer architecture.	SLIP	2004	DBLP DOI BibTeX RDF	wire length estimation, FPGA, reliability, reconfigurability, defect tolerance, nanoelectronics, Rent's rule, nanocomputing
28	Shanrui Zhang, Minsu Choi, Nohpill Park	Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme.	DFT	2004	DBLP DOI BibTeX RDF
28	Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson	The yield enhancement of field-programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
27	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	placement, Microfluidics, biochip
27	Kazuteru Namba, Hideo Ito	Design of Defect Tolerant Wallace Multiplier.	PRDC	2005	DBLP DOI BibTeX RDF
27	Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi	DTR: A Defect-Tolerant Routing Algorithm.	DAC	1989	DBLP DOI BibTeX RDF
24	Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang	Design and defect tolerance beyond CMOS.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	cmol, nanotechnology, defect tolerance, qca, spin wave
24	Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko	BIST Based Interconnect Fault Location for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
22	Vladimir M. Ciric, Vladimir Simic, Ivan Z. Milentijevic	Yield Modeling for Error Tolerant and Partially Defect Tolerant Arrays.	ECBS	2012	DBLP DOI BibTeX RDF
22	Gethin Norman, David Parker 0001, Marta Z. Kwiatkowska, Sandeep K. Shukla	Evaluating the reliability of NAND multiplexing with PRISM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Ethan Schuchman, T. N. Vijaykumar	Rescue: A Microarchitecture for Testability and Defect Tolerance.	ISCA	2005	DBLP DOI BibTeX RDF
22	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
20	Gang Wang 0015, Wenrui Gong, Ryan Kastner	On the use of Bloom filters for defect maps in nanocomputing.	ICCAD	2006	DBLP DOI BibTeX RDF	defect map, nanotechnology, Bloom filter, defect tolerant
17	Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan	Area Reliability Trade-Off in Improved Reed Muller Coding.	SAMOS	2008	DBLP DOI BibTeX RDF
17	Jing Huang 0001, Mariam Momenzadeh, Fabrizio Lombardi	Defect tolerance of QCA tiles.	DATE	2006	DBLP DOI BibTeX RDF	emerging technologies, defect tolerance, QCA
17	Nader Mir-Fakhraei	ATM switching architectures for wafer-scale integration.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
16	Seokjin Oh, Jiyong An, Kyeong-Sik Min	Neuron Deactivation Scheme for Defect-Tolerant Memristor Neural Networks.	MOCAST	2022	DBLP DOI BibTeX RDF
16	Xiaojing Zha, Yinshui Xia, Shang-Luan Xie, Zhufei Chu	Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization.	J. Comput. Sci. Technol.	2021	DBLP DOI BibTeX RDF
16	Mingrui Jiang, Ruibin Mao, John Paul Strachan, Can Li	Defect tolerant in-memory analog computing with CMOS-integrated nanoscale crossbars: Invited.	ICECS	2021	DBLP DOI BibTeX RDF
16	Atin Mukherjee 0001	Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic.	TENCON	2020	DBLP DOI BibTeX RDF
16	Xiaojing Zha, Yinshui Xia	Defect-Tolerant Mapping of CMOL Circuits with Delay Optimization.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
16	Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan	A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
16	Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min	Defect-Tolerant Crossbar Training of Memristor Ternary Neural Networks.	ICECS	2019	DBLP DOI BibTeX RDF
16	Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min	Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing.	ASICON	2019	DBLP DOI BibTeX RDF
16	Atin Mukherjee 0001, Anindya Sundar Dhar	Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy.	iSES	2019	DBLP DOI BibTeX RDF
16	Onur Tunali, Muhammed Ceylan Morgül, Mustafa Altun	Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation.	IEEE Micro	2018	DBLP DOI BibTeX RDF
16	Safa Berrima, Yves Blaquière, Yvon Savaria	Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits.	Integr.	2018	DBLP DOI BibTeX RDF
16	Wenbin Zheng, Anqi Wang, Ping Fu, Hongyuan Jiang	A defect tolerant high level synthesis method for digital microfluidic biochips based on the improved genetic algorithm.	I2MTC	2018	DBLP DOI BibTeX RDF
16	Xiaojing Zha, Yinshui Xia	Genetic algorithm based on divide-and-conquer strategy for defect-tolerant CMOL mapping.	ASICON	2017	DBLP DOI BibTeX RDF
16	Soumya Banerjee 0004, Wenjing Rao	A general approach for highly defect tolerant Parallel Prefix Adder design.	DATE	2016	DBLP BibTeX RDF
16	Arwa Ben Dhia, Mariem Slimani, Hao Cai, Lirida A. B. Naviner	A dual-rail compact defect-tolerant multiplexer.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
16	Atin Mukherjee 0001, Anindya Sundar Dhar	New triple-transistor based defect-tolerant systems for reliable digital architectures.	ISCAS	2015	DBLP DOI BibTeX RDF
16	Teijiro Isokawa, Tadashi Kunieda, Nobuyuki Matsui, Ferdinand Peper	Reconfiguration in Defect-Tolerant Asynchronous Cellular Automata.	CANDAR	2015	DBLP DOI BibTeX RDF
16	Adrien Blanchardon	Synthèse d'architectures de circuits FPGA tolérants aux défauts. (Defect tolerant fpga architecture synthesis).		2015	RDF
16	Bo Yuan 0006, Bin Li 0025, Thomas Weise 0001, Xin Yao 0001	A New Memetic Algorithm With Fitness Approximation for the Defect-Tolerant Logic Mapping in Crossbar-Based Nanoarchitectures.	IEEE Trans. Evol. Comput.	2014	DBLP DOI BibTeX RDF
16	Yehua Su, Wenjing Rao	An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
16	Zheng Li 0006, Frank Lockom, Shangping Ren	Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
16	Yves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria	Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain.	ISCAS	2014	DBLP DOI BibTeX RDF
16	Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner	Comparative study of defect-tolerant multiplexers for FPGAs.	IOLTS	2014	DBLP DOI BibTeX RDF
16	Mariem Slimani, Arwa Ben Dhia, Lirida A. B. Naviner	Cross logic: A new approach for defect-tolerant circuits.	ICICDT	2014	DBLP DOI BibTeX RDF
16	Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner	A defect-tolerant multiplexer using differential logic for FPGAs.	MIXDES	2014	DBLP DOI BibTeX RDF
16	Vasileios Vasilikos, Georgios Smaragdos, Christos Strydis, Ioannis Sourdis	Heuristic search for adaptive, defect-tolerant multiprocessor arrays.	ACM Trans. Embed. Comput. Syst.	2013	DBLP DOI BibTeX RDF
16	Masoud Zamani, Hanieh Mirzaei, Mehdi Baradaran Tahoori	ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures.	ACM J. Emerg. Technol. Comput. Syst.	2013	DBLP DOI BibTeX RDF
16	Arwa Ben Dhia, Samuel N. Pagliarini, Lirida Alves de Barros Naviner, Habib Mehrez, Philippe Matherat	A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Yehua Su, Wenjing Rao	Defect-tolerant logic hardening for crossbar-based nanosystems.	DATE	2013	DBLP DOI BibTeX RDF
16	Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi	A defect-tolerant cluster in a mesh SRAM-based FPGA.	FPT	2013	DBLP DOI BibTeX RDF
16	Ke Yue, Frank Lockom, Zheng Li 0006, Soumia Ghalim, Shangping Ren, Lei Zhang 0008, Xiaowei Li 0001	Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC.	ASP-DAC	2012	DBLP DOI BibTeX RDF
16	Shi-Qing Xin, Dao Thi Phuong Quynh, Xiang Ying, Ying He 0001	A global algorithm to compute defect-tolerant geodesic distance.	SIGGRAPH Asia Technical Briefs	2012	DBLP DOI BibTeX RDF
16	Olivier Temam	A defect-tolerant accelerator for emerging high-performance applications.	ISCA	2012	DBLP DOI BibTeX RDF
16	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	DEFCAM: A design and evaluation framework for defect-tolerant cache memories.	ACM Trans. Archit. Code Optim.	2011	DBLP DOI BibTeX RDF
16	Asbjørn Djupdal, Pauline C. Haddow	The route to a defect tolerant LUT through artificial evolution.	Genet. Program. Evolvable Mach.	2011	DBLP DOI BibTeX RDF
16	Marcel Campen, Leif Kobbelt	Walking On Broken Mesh: Defect-Tolerant Geodesic Distances and Parameterizations.	Comput. Graph. Forum	2011	DBLP DOI BibTeX RDF
16	Pauline C. Haddow	Evolving defect tolerant structures for FPGA architectures.	ACSCC	2011	DBLP DOI BibTeX RDF
16	Yehua Su, Wenjing Rao	Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously.	ICCAD	2011	DBLP DOI BibTeX RDF
16	Vladimir M. Ciric, Aleksandar M. Cvetkovic, Ivan Z. Milentijevic	Yield analysis of partial defect tolerant bit-plane array.	Comput. Math. Appl.	2010	DBLP DOI BibTeX RDF
16	Tao Xu 0002, Krishnendu Chakrabarty, Vamsee K. Pamula	Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
16	Lei Zhang 0008, Yue Yu, Jianbo Dong, Yinhe Han 0001, Shangping Ren, Xiaowei Li 0001	Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.	DATE	2010	DBLP DOI BibTeX RDF
16	Sezer Gören 0001, H. Fatih Ugurdag, Okan Palaz	Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort.	ISCIS	2010	DBLP DOI BibTeX RDF
16	Juan A. Carrasco, Víctor Suñé	An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Lei Zhang 0008, Yinhe Han 0001, Qiang Xu 0001, Xiaowei Li 0001, Huawei Li 0001	On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan	Defect-tolerant n2-transistor structure for reliable nanoelectronic designs.	IET Comput. Digit. Tech.	2009	DBLP DOI BibTeX RDF
16	Yehua Su, Wenjing Rao	Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures.	NANOARCH	2009	DBLP DOI BibTeX RDF
16	Yehua Su, Wenjing Rao	Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis.	DFT	2009	DBLP DOI BibTeX RDF
16	Adit D. Singh	A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.	DFT	2009	DBLP DOI BibTeX RDF
16	Seung-Hoon Tong, Bong-Jin Yum	A dual burn-in policy for defect-tolerant memory products using the number of repairs as a quality indicator.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
16	Kazutoshi Kobayashi, Hidetoshi Onodera	Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
16	Shuo Wang, Jianwei Dai, Lei Wang 0003	Defect-tolerant digital filtering with unreliable molecular electronics.	SiPS	2008	DBLP DOI BibTeX RDF
16	Ali Namazi, M. Nourami, M. Saquib	A voterless strategy for defect-tolerant nano-architectures.	NANOARCH	2008	DBLP DOI BibTeX RDF