Search results for "double-gate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
114	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
105	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang	Nanoscale CMOS circuit leakage power reduction by double-gate device.	ISLPED	2004	DBLP DOI BibTeX RDF	double-gate device, short-channel effect, leakage power
77	Feng Liu, Jin He 0003, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang 0002, Mansun Chan	Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes.	ISQED	2008	DBLP DOI BibTeX RDF	double-gate MOSFET, drain current, compact model
72	Hari Ananthan, Kaushik Roy 0001	A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.	DAC	2006	DBLP DOI BibTeX RDF	leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate
62	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
57	Ru Huang, FaLong Zhou, Yimao Cai, DaKe Wu, Xing Zhang 0002	Novel vertical channel double gate structures for high density and low power flash memory applications.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	double gate devices, high density, low power, flash memory
57	Bastien Giraud, Amara Amara	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.	DELTA	2008	DBLP DOI BibTeX RDF	SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
56	Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
56	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
54	Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun	Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.	ISQED	2008	DBLP DOI BibTeX RDF	static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
48	Paul Beckett	A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
47	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
47	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.	ISQED	2005	DBLP DOI BibTeX RDF
45	Jin He 0003, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu	A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach.	ISQED	2004	DBLP DOI BibTeX RDF
43	Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka	Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
42	Liqiong Wei, Rongtian Zhang, Kaushik Roy 0001, Zhanping Chen, David B. Janes	Vertically integrated SOI circuits for low-power and high-performance applications.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
39	Amara Amara, Bastien Giraud, Olivier Thomas	An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.	DELTA	2010	DBLP DOI BibTeX RDF	SRAM cell, Planar Double-Gate (DG), Fully Depleted SOI (FD-SOI), read and write tradeoffs, Ultra Low Voltage (ULV)
38	Bastien Giraud, Amara Amara, Andrei Vladimirescu	A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
37	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
36	Betty Prince	Nanotechnology and emerging memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory
35	Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
34	Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy 0001	Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Salvador Ivan Garduño, Antonio Cerdeira, Magali Estrada	Gate leakage currents modeling for oxynitride gate dielectric in double gate MOSFETs.	CCE	2011	DBLP DOI BibTeX RDF
33	Paul Beckett	Low-power circuits using dynamic threshold devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate
33	Paul Beckett	Exploiting multiple functionality for nano-scale reconfigurable systems.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	chalcogenide, double gate transistors, multi-valued RAM, multiple functionality, resonant tunneling, nanotechnology, reconfigurable systems, carbon nanotube, nanoelectronics, RTD
30	Bastien Giraud, Amara Amara	A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Olivier Thomas, Marina Reyboz, Marc Belleville	Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar	Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
26	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
26	Bao Liu 0001	Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
25	Dibyendu Chowdhury, Bishnu Prasad De, Bhargav Appasani, Navaneet Kumar Singh, Rajib Kar, Durbadal Mandal, Nicu Bizon, Phatiphat Thounthong	A Novel Dielectric Modulated Gate-Stack Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor-Based Sensor for Detecting Biomolecules.	Sensors	2023	DBLP DOI BibTeX RDF
25	Pavan Kumar, Kosaraju Sivani	Double Gate TFET Simulation with Different Gate Oxides and Thickness.	ICCCNT	2023	DBLP DOI BibTeX RDF
25	Rajesh Saha, Rupam Goswami, Deepak Kumar Panda	Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
25	K. Murali Chandra Babu, Ekta Goel	Analysis of ON Current and Ambipolar Current for Source Pocket Gate-Drain Underlap Double Gate Tunnel Field Effect Transistor.	iSES	2022	DBLP DOI BibTeX RDF
25	Satyendra Kumar	Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual-material gate-oxide-stack double-gate TFET.	IET Circuits Devices Syst.	2021	DBLP DOI BibTeX RDF
25	Priyanka Karmakar, Prasanna Kumar Sahu	Investigation of Dielectric Pocket and Work function Engineering in Triple Material Hetero Gate Stack Oxide Double Gate TFET for Low Power Applications.	TENCON	2021	DBLP DOI BibTeX RDF
25	Shelly Garg, Sneh Saurabh	Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis.	IEEE Access	2019	DBLP DOI BibTeX RDF
25	Nicolo Oliva, Emanuele A. Casu, Matteo Cavalleri, Adrian M. Ionescu	Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control.	ESSDERC	2018	DBLP DOI BibTeX RDF
25	Md. Sazzadur Rahman, Nabil Ahmed	Impact of Gate Underlap Design on Analog and RF Performance for 20nm Tri-Material Double Gate(TMDG) MOSFET.	TENCON	2018	DBLP DOI BibTeX RDF
25	Daniela Munteanu, Jean-Luc Autran, Soilihi Moindjie	Single-event-transient effects in Junctionless Double-Gate MOSFETs with Dual-Material Gate investigated by 3D simulation.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
25	Neha Sharan, Santanu Mahapatra	Compact noise modelling for common double-gate metal-oxide-semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry.	IET Circuits Devices Syst.	2016	DBLP DOI BibTeX RDF
25	Ping Wang, Yiqi Zhuang, Cong Li, Zhi Jiang, Yuqi Liu	Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
25	Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang	Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure.	ASICON	2015	DBLP DOI BibTeX RDF
25	Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma	Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs.	iNIS	2015	DBLP DOI BibTeX RDF
25	Neha Sharan, Santanu Mahapatra	Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry.	VLSID	2014	DBLP DOI BibTeX RDF
25	Angsuman Sarkar, Aloke Kumar Das, Swapnadip De, Chandan Kumar Sarkar	Effect of gate engineering in double-gate MOSFETs for analog/RF applications.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
25	Neha Verma 0003, Jyotika Jogi, Mridula Gupta, R. S. Gupta	Simulation of Enhanced Gate Control in a Double Gate Quantum Domain InAlAs/InGaAs/InP HEMT.	UKSim	2012	DBLP DOI BibTeX RDF
25	Fayçal Djeffal, Toufik Bendib	Multi-objective genetic algorithms based approach to optimize the electrical performances of the gate stack double gate (GSDG) MOSFET.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
25	Viranjay M. Srivastava, Kalyan S. Yadav, Ghanshyam Singh	Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
25	Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta	Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
25	Fayçal Djeffal, Toufik Bentrcia, Mohamed Amir Abdi, Toufik Bendib	Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
25	Swagata Bhattacherjee, Abhijit Biswas	Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
25	Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta	Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
25	S. Kolberg, H. Børli, Tor A. Fjeldly	Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs.	Math. Comput. Simul.	2008	DBLP DOI BibTeX RDF
25	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy 0001	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.	Microelectron. J.	2007	DBLP DOI BibTeX RDF
23	Malvika, Jagritee Talukdar, Bijit Choudhuri, Kavicharan Mummaneni	A simulation study of the effect of ferroelectric thickness and oxide variation on the performance of Highly Doped Double Pocket Double Gate NCFET based inverter.	iSES	2022	DBLP DOI BibTeX RDF
23	Neha Verma 0003, Parveen, Jyotika Jogi	Quantum Simulation of a Double Gate Double Heterostructure in AlAs/InGaAs HEMT to Analyze Temperature Effects.	UKSim	2015	DBLP DOI BibTeX RDF
23	Viranjay M. Srivastava, Kalyan S. Yadav, Ghanshyam Singh	Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch.	Wirel. Eng. Technol.	2011	DBLP DOI BibTeX RDF
23	Viranjay M. Srivastava	Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology.	Wirel. Eng. Technol.	2010	DBLP DOI BibTeX RDF
23	Ratul Kumar Baruah, Santanu Mahapatra	Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Paul Beckett, Heiko Rudolph	Run.	DELTA	2010	DBLP DOI BibTeX RDF	low power computer architecture, modeling, SOI, VHDL-AMS, double gate
23	Sudipta Sarkar, Ananda S. Roy, Santanu Mahapatra	A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET.	VLSI Design	2010	DBLP DOI BibTeX RDF	Non Quasi-Static Analysis, Double-Gate MOSFET
23	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
23	Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic	FinFET-based SRAM design.	ISLPED	2005	DBLP DOI BibTeX RDF	double gate transistors, low power, memory, SRAM
19	Wei Zhao, Yu Cao 0001	Predictive technology model for nano-CMOS design exploration.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	early design exploration, process variations, predictive modeling, Technology scaling, FinFET
19	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
18	Mohab Anis	Advanced IC technology - opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu	Leakage-Aware Design of Nanometer SoC.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot	Novel CNTFET-based Reconfigurable Logic Gate Design.	DAC	2007	DBLP DOI BibTeX RDF
16	K. Manikanta, Umakanta Nanda, Chandan Kumar Pandey	Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
16	Zohmingliana, Bijit Choudhuri, Brinda Bhowmick	Design of Dual-Band Rectifier Circuit for RF Energy Harvesting Using Double-Gate Graphene Nanoribbon (GNR) Vertical Tunnel FET.	IEEE Trans. Consumer Electron.	2024	DBLP DOI BibTeX RDF
16	Mohammad Khaleqi Qaleh Jooq, Fereshteh Behbahani, Mohammad Hossein Moaiyeri	Ultra-efficient fully programmable membership function generator based on independent double-gate FinFET technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
16	Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar	Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Adrija Mukherjee, Papiya Debnath, D. Nirmal, Manash Chanda	A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Karabi Baruah, Srimanta Baishya	Numerical assessment of dielectrically-modulated short- double-gate PNPN TFET-based label-free biosensor.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Dasari Srikanya, Aasif Mohammad Bhat, Chitrakant Sahu	Design and analysis of high-performance double-gate ZnO nano-structured thin-film ISFET for pH sensing applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Manas Pratap, Harshit Kansal, Aditya Sankar Medury	Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Prajvi Udar, Anubha Goel, R. S. Gupta	Nanoscale Temperature Dependent Quantum-Effect Analytical Model of Short- Channel, Junction-Less, Double-Gate Stack (SC-JL-DG) MOSFET for Analog Applications at Higher Frequencies.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Deep Shekhar, Ashish Raman	Study of ambipolar and linearity behavior of the misaligned double gate-drain dopant-free Nano-TFET: Design and performance enhancement.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Prajvi Udar, Anubha Goel, R. S. Gupta	Quantum Effect Dependent Modelling of Short Channel Junctionless Double Gate Stack(SC-JL-DG) MOSFET for High Frequency Analog Applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Liu Liu, Shubham Kumar, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch, Xiaobo Sharon Hu	Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs.	CoRR	2023	DBLP DOI BibTeX RDF
16	Xingchen Xin, Chunsheng Jiang, Hongying Chen	A Continuous and Closed-Form Trans-Capacitance Model for Double-Gate Junctionless Transistors.	ASICON	2023	DBLP DOI BibTeX RDF
16	Mbalenhle Mngomezulu, Viranjay M. Srivastava	Gain Analysis of Prototyped Wilson Current Mirror Using Double-Gate MOSFET.	SSD	2023	DBLP DOI BibTeX RDF
16	Tika Ram Pokhrel, Alak Majumder	Double Gate JLT Based New TIGFET for Dynamic C2MOS Application.	APCCAS	2023	DBLP DOI BibTeX RDF
16	Liu Liu, Shubham Kumar, Simon Thomann, Hussam Amrouch, Xiaobo Sharon Hu	Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs.	DAC	2023	DBLP DOI BibTeX RDF
16	Naveenbalaji Gowthaman, Viranjay M. Srivastava	Design of Cylindrical Surrounding Double-Gate MOSFET With Fabrication Steps Using a Layer-by-Layer Approach.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Deepjyoti Deb, Rupam Goswami, Ratul Kr. Baruah, Kavindra Kandpal, Rajesh Saha	Parametric investigation and trap sensitivity of n-p-n double gate TFETs.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
16	Gargi Jana, Dipanjan Sen, Papiya Debnath, Manash Chanda	Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
16	Damodhar Rao M., Y. V. Narayana, V. V. K. D. V. Prasad	Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells.	Sustain. Comput. Informatics Syst.	2022	DBLP DOI BibTeX RDF
16	Xuguo Zhang, Jie Xu, Zixin Chen, Qiuhui Wang, Weijing Liu, Qinghua Li, Wei Bai, Xiadong Tang	Investigation and optimization of electro-thermal performance of Double Gate-All-Around MOSFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
16	Banoth Vasu Naik, Arun Kumar Sinha	RF and Linearity Analysis of a Symmetrical Junction Non-Aligned Double Gate FET Device.	ICM	2022	DBLP DOI BibTeX RDF
16	Banoth Vasu Naik, Arun Kumar Sinha	Nano Design of a Symmetrical Junction Non-Aligned Double Gate FET Device with Improved Analog Figure of Merit.	ICM	2022	DBLP DOI BibTeX RDF
16	Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni 0004	Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
16	Kallepelli Sagar, Satish Maheshwaram	Performance Comparison of Circular Double Gate Transistor (CDGT) with Novel Architectures for High-Performance Applications.	iSES	2022	DBLP DOI BibTeX RDF
16	Srinivas Varma, Ch Pratyusha Chowdari, D. Jayanthi, Asisa Kumar Panigrahi, K. Jamal	TCAD Simulation of a 10nm n-Channel Vertical Double Gate Silicon On Insulator MOSFET for Digital Applications.	ICCCNT	2022	DBLP DOI BibTeX RDF
16	U. S. Shikha, Rekha K. James, Anju Pradeep, Sumi Baby, Jobymol Jacob	Threshold Voltage Modeling of Negative Capacitance Double Gate TFET.	VLSID	2022	DBLP DOI BibTeX RDF
16	Maduagwu Anthony Uchechukwu, Viranjay M. Srivastava	Sensitivity of Lightly and Heavily Dopped Cylindrical Surrounding Double-Gate (CSDG) MOSFET to Process Variation.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Pattunnarajam Paramasivam, Naveenbalaji Gowthaman, Viranjay M. Srivastava	Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs With La2O3 for 5-nm Technology.	IEEE Access	2021	DBLP DOI BibTeX RDF