Search results for "glitch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Fei Hu, Vishwani D. Agrawal	Input-specific dynamic power optimization for VLSI circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic power optimization, glitch reduction, input specific
86	Scott Cromar, Jaeho Lee, Deming Chen	FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.	DAC	2009	DBLP DOI BibTeX RDF	glitch power, FPGA, high-level synthesis, power reduction
86	Fei Hu, Vishwani D. Agrawal	Dual-transition glitch filtering in probabilistic waveform power estimation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-transition probability, dynamic power estimation, glitch filtering, probabilistic waveform simulation
80	Quang Dinh, Deming Chen, Martin D. F. Wong	A routing approach to reduce glitches in low power FPGAs.	ISPD	2009	DBLP DOI BibTeX RDF	glitch reduction, path balancing, fpgas, routing, low power
62	Yuanlin Lu, Vishwani D. Agrawal	Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
62	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF
52	David Naccache, Phong Q. Nguyen, Michael Tunstall, Claire Whelan	Experimenting with Faults, Lattices and the DSA.	Public Key Cryptography	2005	DBLP DOI BibTeX RDF	glitch attacks, fault injection, lattice reduction, DSA
48	Biwei Liu, Shuming Chen, Hu Xiao	Analysis of Glitch Reconvergence in Combinational Logic SER Estimation.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Reconvergence, SER esitmation, SET
48	Yijun Zhou, Jiren Yuan	An 8-Bit, 100-MHz low glitch interpolation DAC.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
43	Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di	Glitch-free design for multi-threshold CMOS NCL circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
43	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
42	Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh	A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.	CHES	2009	DBLP DOI BibTeX RDF
42	Benoit Catteau, Pieter Rombouts, Ludo Weyten	A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault tolerant clockless wave pipeline design.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability
42	N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das	Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
39	Daniel Lammers, Nicolai Müller, Amir Moradi 0001	Glitch-free is not Enough - Revisiting Glitch-Extended Probing Model.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
39	Bahram Rashidi	Glitch-less hardware implementation of block ciphers based on an efficient glitch filter.	Integr.	2022	DBLP DOI BibTeX RDF
39	Patricia S. Gracia	Las consecuencias del glitch en el entorno virtual interactivo(The consequences of the glitch in the interactive virtual environment).	CoSECivi	2020	DBLP BibTeX RDF
39	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
39	Rudolfo Quintas	Glitch Delighter: Lighter's Flame Base Hyper-Instrument for Glitch Music in Burning The Sound Performance.	NIME	2010	DBLP DOI BibTeX RDF
39	Daisuke Suzuki, Koichi Shimizu	The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.	CHES	2010	DBLP DOI BibTeX RDF
38	Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001	Static Crosstalk Noise Analysis with Transition Map.	DELTA	2008	DBLP DOI BibTeX RDF	static noise analysis, crosstalk, glitch
34	Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.	ASP-DAC	2008	DBLP DOI BibTeX RDF
34	Ahmed Sayed, Hussain Al-Asaad	A New Statistical Approach for Glitch Estimation in Combinational Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	42% power savings through glitch-reducing clocking strategy in a hearing aid application.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Yuanlin Lu, Vishwani D. Agrawal	Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.	PATMOS	2005	DBLP DOI BibTeX RDF
34	Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez	Glitch-free discretely programmable clock generation on chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
34	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Glitch power minimization by selective gate freezing.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
34	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Glitch Power Minimization by Gate Freezing.	DATE	1999	DBLP DOI BibTeX RDF
28	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
28	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas	Probabilistic gate-level power estimation using a novel waveform set method.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	probabilistic power estimation, probability waveform, transition density, combinational logic, gate-level
28	Lei Cheng 0001, Deming Chen, Martin D. F. Wong	GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.	DAC	2007	DBLP DOI BibTeX RDF
28	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Modeling of Crosstalk Fault in Defective Interconnects.	PATMOS	2006	DBLP DOI BibTeX RDF	defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards
28	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.	DFT	2006	DBLP DOI BibTeX RDF	defective interconnects, defect’s severity, fault model, crosstalk, bridging fault
28	Seong-Min Ha, Tae-Kyu Nam, Kwang S. Yoon	An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Variable Input Delay CMOS Logic for Low Power Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
28	Sarah Thompson, Alan Mycroft	Abstract Interpretation of Combinational Asynchronous Circuits.	SAS	2004	DBLP DOI BibTeX RDF
28	Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, Seung-Hoon Lee	A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
28	J. H. Wang	Event-overlapping processing in current waveform simulation.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
24	Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu 0001, Byron Krauter	A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.	DAC	2005	DBLP DOI BibTeX RDF	glitch propagation, noise analysis, effective capacitance
24	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
24	Joseph N. Kozhaya, Farid N. Najm	Accurate power estimation for large sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	power vector set, simulation, VLSI, CAD, dynamic, power, correlation, estimation, Monte Carlo, compaction, sequential, glitch
24	Daniel Brand, Chandramouli Visweswariah	Inaccuracies in power estimation during logic synthesis.	ICCAD	1996	DBLP DOI BibTeX RDF	glitch power, simulation, logic synthesis, power estimation, power optimization
24	Thomas J. Chaney	Comments on "A Note on Synchronizer or Interlock Maloperation".	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	flip-flop metastability, interrupt failure, Arbiter, glitch, asynchronous interactions, synchronizer failure
24	George R. Couranz, Donald F. Wann	Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Asynchronous fundamental mode input changes, binary switching time, flip-flop metastable region, interrupt failure, probabilistic behavior of flip-flops, glitch, asynchronous interactions, synchronizer failures
20	Talal Bonny, Farah AlMutairi, Wafaa Al Nassan	A novel clock-glitch-attack-proof image encryption algorithm implemented on FPGA.	Multim. Tools Appl.	2024	DBLP DOI BibTeX RDF
20	Tom Dooney, Lyana Curier, Daniel Stanley Tan, Melissa Lopez, Chris Van Den Broeck, Stefano Bromuri	cDVGAN: One Flexible Model for Multi-class Gravitational Wave Signal and Glitch Generation.	CoRR	2024	DBLP DOI BibTeX RDF
20	Amund Askeland, Svetla Nikova, Ventzislav Nikov	Who Watches the Watchers: Attacking Glitch Detection Circuits.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2024	DBLP DOI BibTeX RDF
20	Marc Schink, Alexander Wagner, Felix Oberhansl, Stefan Köckeis, Emanuele Strieder, Sven Freud, Dominik Klein 0001	Unlock the Door to my Secrets, but don't Forget to Glitch A comprehensive analysis of flash erase suppression attacks.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2024	DBLP DOI BibTeX RDF
20	Amélie Marotta, Ronan Lashermes, Guillaume Bouffard, Olivier Sentieys, Rachid Dafali	Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.	COSADE	2024	DBLP DOI BibTeX RDF
20	Osman Tayfun Biskin, Ismail Kirbas, Ali Çelik	A fast and time-efficient glitch classification method: A deep learning-based visual feature extractor for machine learning algorithms.	Astron. Comput.	2023	DBLP DOI BibTeX RDF
20	Zhixi Cai, Shreya Ghosh 0001, Abhinav Dhall, Tom Gedeon, Kalin Stefanov, Munawar Hayat	Glitch in the matrix: A large scale benchmark for content driven audio-visual forgery detection and localization.	Comput. Vis. Image Underst.	2023	DBLP DOI BibTeX RDF
20	Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan	Geometric Programming Approach to Glitch Minimization via Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
20	Zhixi Cai, Shreya Ghosh 0001, Abhinav Dhall, Tom Gedeon, Kalin Stefanov, Munawar Hayat	"Glitch in the Matrix!": A Large Scale Benchmark for Content Driven Audio-Visual Forgery Detection and Localization.	CoRR	2023	DBLP DOI BibTeX RDF
20	Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi	Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M.	CoRR	2023	DBLP DOI BibTeX RDF
20	Giovanni Monea, Maxime Peyrard, Martin Josifoski, Vishrav Chaudhary, Jason Eisner, Emre Kiciman, Hamid Palangi, Barun Patra, Robert West 0001	A Glitch in the Matrix? Locating and Detecting Language Model Grounding with Fakepedia.	CoRR	2023	DBLP DOI BibTeX RDF
20	Jamal Knight, Andrew Johnston, Adam Berry	Artistic control over the glitch in AI-generated motion capture.	CoRR	2023	DBLP DOI BibTeX RDF
20	Nuno Saavedra, João Gonçalves, Miguel Henriques, João F. Ferreira 0001, Alexandra Mendes	Polyglot Code Smell Detection for Infrastructure as Code with GLITCH.	CoRR	2023	DBLP DOI BibTeX RDF
20	Fu Yao, Hua Chen, Yongzhuang Wei, Enes Pasalic, Feng Zhou, Limin Fan	Optimizing AES Threshold Implementation under the Glitch-Extended Probing Model.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
20	Amund Askeland, Svetla Nikova, Ventzislav Nikov	Who Watches the Watchers: Attacking Glitch Detection Circuits.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
20	Weifeng Liu, Tianxiao Zhang, Hanchen Zhang, Hualian Tang, Li Zhang	A glitch energy reduction method with low complexity dynamic element matching for data converters.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
20	Mickey Mengting Zhang, Yu Shen, Ihab Salah Ali Mohamed	Visualizing Ocean Fragility: Glitch Art and Social Media in Marine Conservation.	HCI (45)	2023	DBLP DOI BibTeX RDF
20	Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri	Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection.	CARDIS	2023	DBLP DOI BibTeX RDF
20	Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi	Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M.	USENIX Security Symposium	2023	DBLP BibTeX RDF
20	Xiaoyun Liang 0006, Jiayi Qi, Yongqiang Gao, Chao Peng, Ping Yang	AG3: Automated Game GUI Text Glitch Detection Based on Computer Vision.	ESEC/SIGSOFT FSE	2023	DBLP DOI BibTeX RDF
20	Noriki Amano	Glitch Art Generation and Performance Using Musical Live Coding.	ArtsIT (2)	2023	DBLP DOI BibTeX RDF
20	Nuno Saavedra, João Gonçalves, Miguel Henriques, João F. Ferreira 0001, Alexandra Mendes	Polyglot Code Smell Detection for Infrastructure as Code with GLITCH.	ASE	2023	DBLP DOI BibTeX RDF
20	Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa	Security Evaluation of Glitch Based Authentication Function for Edge AI.	GCCE	2023	DBLP DOI BibTeX RDF
20	Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu	Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
20	Jianqi Yan, Alex P. Leung, David C. Y. Hui	On Improving the Performance of Glitch Classification for Gravitational Wave Detection by using Generative Adversarial Networks.	CoRR	2022	DBLP DOI BibTeX RDF
20	Nuno Saavedra, João F. Ferreira 0001	GLITCH: an Intermediate-Representation-Based Security Analysis for Infrastructure as Code Scripts.	CoRR	2022	DBLP DOI BibTeX RDF
20	Benedikte Wallace, Charles P. Martin	Embodying the Glitch: Perspectives on Generative AI in Dance Practice.	CoRR	2022	DBLP DOI BibTeX RDF
20	Pablo Morales-Álvarez, Pablo Ruiz 0002, Scott Coughlin, Rafael Molina 0001, Aggelos K. Katsaggelos	Scalable Variational Gaussian Processes for Crowdsourcing: Glitch Detection in LIGO.	IEEE Trans. Pattern Anal. Mach. Intell.	2022	DBLP DOI BibTeX RDF
20	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Gate-Level RTL Description of the Glitch Optimized Multipliers.		2022	DOI RDF
20	Tahmida Islam, Junkyu Kim, Chris H. Kim, David Tipple, Michael Nelson, Robert Jin, Anis Jarrar	A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal.	IRPS	2022	DBLP DOI BibTeX RDF
20	Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray	An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
20	Aaron Juarez	Glitch Serendipity: Alternative Information Seeking that Leads to Discovery.	Creativity & Cognition	2022	DBLP DOI BibTeX RDF
20	Nuno Saavedra, João F. Ferreira 0001	GLITCH: Automated Polyglot Security Smell Detection in Infrastructure as Code.	ASE	2022	DBLP DOI BibTeX RDF
20	Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo	A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
20	Hossein Ghasemian, Amin Bahrami, Ebrahim Abiri, Mohammad Reza Salehi	A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
20	Xiaoke Tang, Xu Zhao, Ang Hu, Dongsheng Liu, Zirui Jin	A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
20	Robert Buhren, Hans Niklas Jacob, Thilo Krachenfels, Jean-Pierre Seifert	One Glitch to Rule Them All: Fault Injection Attacks Against AMD's Secure Encrypted Virtualization.	CoRR	2021	DBLP BibTeX RDF
20	Reymond Mesuga, Brian James Bayanay	On the Efficiency of Various Deep Transfer Learning Models in Glitch Waveform Detection in Gravitational-Wave Data.	CoRR	2021	DBLP BibTeX RDF
20	Jürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001, Matthias Függer, Thomas Nowak	A Composable Glitch-Aware Delay Model.	CoRR	2021	DBLP BibTeX RDF
20	Wenye Liu, Chip-Hong Chang, Fan Zhang 0010	Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint.	IEEE Trans. Inf. Forensics Secur.	2021	DBLP DOI BibTeX RDF
20	Gaëtan Cassiers, François-Xavier Standaert	Provably Secure Hardware Masking in the Transition- and Glitch-Robust Probing Model: Better Safe than Sorry.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2021	DBLP DOI BibTeX RDF
20	Robert Buhren, Hans Niklas Jacob, Thilo Krachenfels, Jean-Pierre Seifert	One Glitch to Rule Them All: Fault Injection Attacks Against AMD's Secure Encrypted Virtualization.	CCS	2021	DBLP DOI BibTeX RDF
20	Stan Verbeek, Tom Oomen, Arnfinn Aas Eielsen	Glitch Compensation for a Digital-to-Analogue Converter.	ACC	2021	DBLP DOI BibTeX RDF
20	Takumi Hayashi, Hiroshi Fujimoto, Yoshihiro Isaoka, Yuki Terada	Negative Quadrant Glitch Suppression of Ball-screw-driven Stage by Initial Value Compensation with Additional Input.	AMC	2021	DBLP DOI BibTeX RDF
20	Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa	Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7.	ISDCS	2021	DBLP DOI BibTeX RDF
20	Joseph Gilling	Haunted by the Glitch: Technological Malfunction - Critiquing the Media of Innovation.	ARTECH	2021	DBLP DOI BibTeX RDF
20	Jürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001, Matthias Függer, Thomas Nowak	A Composable Glitch-Aware Delay Model.	ACM Great Lakes Symposium on VLSI	2021	DBLP DOI BibTeX RDF
20	Li Ni, Pengjun Wang, Yuejun Zhang, Jia Chen, Liwei Li 0004, Huihong Zhang	A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security.	ASICON	2021	DBLP DOI BibTeX RDF
20	Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu	Formal Evaluation and Construction of Glitch-resistant Masked Functions.	HOST	2021	DBLP DOI BibTeX RDF
20	Yusuke Nozaki, Masaya Yoshikawa	Neural Network Based Glitch Physically Unclonable Function.	UEMCON	2021	DBLP DOI BibTeX RDF
20	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
20	Stephanie T. Jones, Natalie Melo	'Anti-blackness is no glitch': the need for critical conversations within computer science education.	XRDS	2020	DBLP DOI BibTeX RDF
20	Dorian Amiet, Lukas Leuenberger, Andreas Curiger, Paul Zbinden	FPGA-based SPHINCS+ Implementations: Mind the Glitch.	DSD	2020	DBLP DOI BibTeX RDF
20	Steffen Zeidler 0001, Oliver Schrape, Anselm Breitenreiter, Milos Krstic	A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks.	DSD	2020	DBLP DOI BibTeX RDF
20	Yusuke Nozaki, Masaya Yoshikawa	Unrolled PRINCE Cipher based Glitch Physically Unclonable Function.	ICISS	2020	DBLP DOI BibTeX RDF