Results
Found 12 publication records. Showing 12 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Hitoshi Oi |
On the design of the local variable cache in a hardware translation-based java virtual machine. |
LCTES |
2005 |
DBLP DOI BibTeX RDF |
hardware-translation, memory hierarchy, java virtual machine |
39 | Ramesh Radhakrishnan, Ravi Bhargava, Lizy Kurian John |
Improving Java performance using hardware translation. |
ICS |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Hitoshi Oi |
Instruction folding in a hardware-translation based java virtual machine. |
Conf. Computing Frontiers |
2006 |
DBLP DOI BibTeX RDF |
hardware-translation, instruction folding, performance evaluation, java virtual machine |
31 | Xiangrong Zhou, Peter Petrov |
Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Xiangrong Zhou, Peter Petrov |
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. |
ACM SIGOPS Oper. Syst. Rev. |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Zi Yan, Guilherme Cox, Ján Veselý, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
12 | Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. |
ISCA |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Hitoshi Oi |
Instruction Folding in a Hardware-Translation Based Java Virtual Machine. |
J. Instr. Level Parallelism |
2008 |
DBLP BibTeX RDF |
|
12 | Hitoshi Oi |
Local variable access behavior of a hardware-translation based Java virtual machine. |
J. Syst. Softw. |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang 0001 |
Processor Mechanisms for Software Shared Memory. |
ISHPC |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni |
From Specification to Hardware Device: A Synthesis Algorithm. |
ICFEM |
2003 |
DBLP DOI BibTeX RDF |
Rapid System Prototyping, Synthesis, Hardware Design |
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